考慮電晶體打摺的先進製程標準電路佈局自動產生器

Abstract

隨著製程的演進，以及製程的規範越趨嚴謹，完全依靠人力來處理佈局圖已漸漸無法負荷。而在不同情況下，像是目標設定在省電或是高速也需要不同的佈局方式；適合的佈局圖產生也需要經過嚴密的模擬，如電阻電容萃取、繞線能力分析。因此在先進製程中搭配程式來做參數化處理處理佈局圖變成是重要的一環。在先進製程的製程規範限制下，使得佈局圖擁有更多的規則性，這些規則性使得程式更加能夠分析。 而本論文是基於現有佈局圖分析其規律性的式樣，將其元件當作基礎元件，推廣至各式各樣組合的佈局圖。雖然在學術界上已有許多自動化標準電路佈局器，如[2]為當初相當具有代表性的作品，在許多標準電路下甚至能產生出比有經驗的佈局工程師更好的結果；但在先進製程下，鮮少有作品討論自動化標準電路佈局器。論文中我們以先進製程標準電路佈局器為主軸，並特別針對電晶體打摺技巧加以討論與分析，讓電晶體打摺後的佈局圖可以達到最佳的擴散區共用。在實驗中，我們的佈局器可以產生出大部分的組合電路佈局圖，並且佈局面積可以與有經驗的佈局工程師相近；並且在電晶體打摺的部分可以維持原始佈局圖的拓樸，以及最佳的擴散區共用。

As semiconductor manufacturing technology advances and the demands of design for manufacturing (DFM) increases greatly, and the design rule set becomes much more complicated than before. It requires huge manpower and design time to manipulate the layout manually. Furthermore, different objectives, such as low power driven or high performance driven designs, require different layout design style to fit different constraints. As various portable devices appear and become popular, to fit the demands of various design constraints, each type of cell is designed to have many versions of different properties in timing delay or power, which implies the potential benefits of automating the cell layout design. Additionally modern complex design rule set imposes too many restrictions on layout design such that regular layout style becomes a mainstream in layout design, making synthesizing cell layout feasible. All of these encourage the development of cell layout synthesis tool. The main concept of the proposed cell layout generator is to utilize a set of regular layout patterns to assemble all cell layouts. And there are some works do the cell layout generator considering DFM which will take yield into consideration. The experimental result shows that we can generate almost all the combinational standard cell layout with similar quality (including timing delay and area) to handcrafted layout. For the problem of transistor folding, we can complete most cases of diffusion sharing.