40奈米製程技術操縱在低電壓的 256Kb 8T 雙埠隨機存取記憶體

Abstract

雙埠隨機存取記憶體因為有雙埠的特性，被廣泛的運用在繪圖晶片和多媒體處理中。雙埠的特性就是指說，雙向隨機存取記憶體可以讓電腦的中央處理器在做圖片運算的同時讓硬體輸出圖片到螢幕上。由於可攜式裝置激烈的成長，為了能夠延長可攜式裝置電池的使用長度，低功率設計已經成為近年來的主流，降低操作電壓是最有效率能夠降低動態功率消耗的方法。然而，雙埠隨機存取記憶體因為其雙埠的特性關係，導致操作電壓降不下來，主要是當兩個埠同時操作在同一個列時，兩個埠都互相干擾彼此，這種來自另一個埠的干擾就是雙埠隨機操作記憶體無法讓操作電壓降低的主要原因。本篇論文的主要目的就是提出新的電路設計來消除來自另一個埠的干擾，讓雙埠隨機存取記憶體能夠在低壓操作，我們提出兩個新的輔助寫入WA4Tx2-4N和WA4Tx2-2P2N來消除干擾，並且降低了100mV的操作電壓，另外還有一個讀寫輔助RWA5T來增強雙埠隨機操作記憶體的讀取和寫入的能力，並降低了120mV的操作電壓；此外，為了增加雙埠隨機記憶體的穩定性，我們提出XCWLUD和CSBLUD來增加其在讀取時的穩定性，經過量測，在0.88V且常溫25℃，良率因為XCWLUD和CSBLUD分別有40.6%和69.1%的改善，並且，所有提出的新設計都可以運用在同步和非同步的相位中。

Dual-port static random access memory (DP-SRAM) has been widely used in graphics chip and media processing because of its multiple access behavior. The DP-SRAM can allow computer CPU to draw the image at the same time that video hardware is reading out to screen. Due to the explosion growth of portable devices, low power design that is crucial key to extend the battery life is becoming main stream over the last few years. A simple way to decrease the dynamic power consumption is to lower the supply voltage down. However, DP-SRAM cell suffers disturbance from dummy read operation induced by the other port when two-port access same row simultaneously. Such disturbance is main reason that prevents DP-SRAM cell from lowering supply voltage down. The main objective of this thesis is to eliminate such disturbance to lower supply voltage down. This thesis proposes two novel write-assists (WA4Tx2-4N and WA4Tx2-2P2N) to mitigate the disturbance and improved VDDmin about 100mV. Plus, another read-write-assist (RWA5T) to enhance read-/write-ability and improved VDDmin about 120mV. Besides, two read-assists (XCWLUD and CSBLUD) are designed to stabilize the DP-SRAM cell from data flipping. The die measurement result shows pass rate is improved about 40.6% by XCWLUD and 69.1% by CSBLUD at 0.88V. All of proposed assistance circuit are support for synchronous and asynchronous clock.