瑕疵導向的工業用測試流程

Abstract

由於現代科技產品對於可靠性的要求大為提升,且傳統的測試方法 如 stuck at, transition, 或 small delay 有其測試的盲點,新的測試技術例 如 Gate-Exhaustive, N-Detect, 或 Cell aware testing 不斷的被提出。雖然 這些新技術可以提升錯誤的涵蓋率,但是也會大量的增加測試的成本, 也就是測試的資料數量。在這邊論文中,提出了瑕疵導向的測試方法。 本方法會先分析實際電路的設計圖,找出可能的物理損壞,並且透過 電路模擬軟體,分析出實際損壞時的類比行為。透過這些分析電路模 型,我們將可以透過可靠的商業軟體產生基於瑕疵行為表現的測試資 料。最後,結合先前建立的瑕疵表現模型,本流程會分析測試資料, 試著刪減測試資料數量。本方法中可以在增加瑕疵測試涵蓋綠的同時, 不會增加太多的測試資料。本流程的後半部,亦可直接應用在商用軟 體所產生的測試資料上,減少其所產生出來的測試資料數量。本實驗 被測試於台灣積體電路的 65 奈米製程,共 845 個標準原件庫上。並且 將測試資料刪減的方法,應用在學術,以及工業,電路上,一個電路 中將會有超過 180 萬個瑕疵被模擬,並且平均可以刪減 70% 的測試資 料。

As the modern ICs are facing increasingly tougher DPPM requirements, and the insufficient of the traditional fault model in testing intra-cell defects, new testing techniques such as Gate-Exhaustive, N-Detect, or Cell-aware were proposed. Though the fault coverage can be improved by these methods, the pattern count, which is the main cost of testing, would be significantly in- creased. In this thesis, a defect aware testing flow for industrial design is presented. The Flow, can target the actual root cause of intra-cell defects while not adding too much patterns and could increase the defect coverage. The rear half of the flow is the proposed methodology which can be applied independently to the state-of-the-art commercial tool to reduce the generated patterns. The newly proposed pattern reduction methodology and the cell- aware testing flow have been evaluated with tsmc 65nm technology on 845 library cells and both ISCAS and real industrial design with up to 1.8 mil- lion defects. The experiment result shows an average reduction of 70% in the pattern count without sacrificing the defect coverage.