類比佈局合成之最佳化與設計遷徙自動化研究

Abstract

數位電路的電腦輔助工具之發展已經數年有餘並且極有所成，然而類比方面的電路則不然，有相當大的改善空間。而隨著製程技術的演進，為了增進製程再利用的程度，設計遷移開始變成受歡迎的問題。藉著之前的研究成果，如擺置的遷移還有繞線資訊的保存，使得我們可以更進一步地去提升性能，我們認為線路的電阻與電容值很可能會對電路的性能帶來影響，所以利用改變線寬的方式去實現增進性能這件事。我們設計了一個流程，它可以藉著改變線寬以提高電路性能並且全自動地產生一組新的佈局同時通過電路驗證，於是電路分析的過程或者是設計流程就能因此加速。我們應用了貪婪啟發式與模擬退火法去最佳化性能在該流程中，此外，該流程能幫助類比佈局合成流程運行得更有效率。

The development of the computer-aided-design (CAD) tools for digital circuits has been perfected for these years. However, the CAD tools for analog circuits still remains a great deal of challenges. Since the size of transistors scales down as the process technology advances, design migration problem takes place to increase the degree of layout reusing. With previous work such as placement migration and routing preservation tool, further performance boost becomes the next step. We aim at the width of wires that impacts resistance and capacitance of wires so as to improve the performance. We implement a flow, which can further improve the performance, generate the modified layout automatically and pass the verification check, to speed up the analysis process or design flow by adjusting the wire width. We apply greedy heuristic and simulated annealing algorithm in our framework. Our flow can help with the analog layout synthesis flow in more efficient way.