一個在數位佈局階段整合擺放及繞線的快速雛型產生器

Abstract

由於電晶體的數量增加，繞線擁擠已成為現今客製數位設計中的關鍵問題。然而，許多研究都致力於在擺放階段解決這個問題，甚至在後來的繞線階段。然而，根據最近的可繞性導向擺放競賽[1-3]，繞線擁擠仍然沒有完全被任何擺放程式解決。因此，在早期階段減輕繞線擁擠有助於解決此問題。在本篇論文中，我們採用了SimPL[4]的架構，以及研究每個參數對於最終結果在半週線長(HPWL)方面的影響，進而發現品質和執行時間最好比例。之後，我們採用了非常快速的繞線器進行繞線。繞線擁擠估計的結果可以作為晶片設計的參考。因此，設計工程師們能夠更早地在平面規劃階段辨識出繞線擁擠的區域，進而改良設計。我們所提出的架構可以在五分鐘之內，交付超過一百萬標準元件的設計繞線擁擠估計的結果。

Routing congestion has become a critical issue in modern custom digital design as the number of transistors increased. However, many researches are dedicated in solving this problem in placement stage or even later in routing stage. Yet, according to recent routability-driven placement contest [1{3], routing congestion is still not perfectly solved by any placer. Therefore, relieving routing congestion in the early stage may help solve the problem. In this work, we adopt the placement framework in SimPL [4] and investigate how does each implementation parameter impacts the quality of ?nal placement result in terms of half-perimeter wirelength (HPWL) and ?nd the best ratio of quality over runtime. We then apply a very fast global router to roughly route the design. The reported over ow result then can be served as a guideline for designers. Consequently, designers are able to identify routing congestions earlier in oorplan stage and improve the design. Our proposed framework can deliver the routing congestion estimation to the designers on the design over one million standard cells within ?ve minutes.