高介電係數 /金屬閘極製程之靜電放電防護設計與研究

Abstract

隨著製程的演進，元件的尺寸不斷的縮小，金氧半場效電晶體的閘極(gate)氧化層厚度越來越薄，以達到積體電路操作速度快以及低功耗的目的，然而，外在環境的靜電並沒有減少，雖然在50奈米以下的製程已經引入了高介電係數的材質以提高等效的氧化層厚度(Effective Oxide Thickness, EOT)，然而元件對靜電的敏感度依舊很高，使得靜電放電(Electrostatic Discharge, ESD)防護成為先進製程中很重要的可靠度議題之一。 為了釋放高能量的靜電電流，在電晶體中寄生的雙極性電晶體(Bipolar Junction Transistor, BJT)扮演著重要的角色，在全晶片靜電放電防護架構中，於輸入/輸出(I/O)腳位(pin)和VDD電源線間使用閘極接VDD之P型金氧半場效電晶體(gate-VDD PMOS, GDPMOS)，以及在輸入/輸出腳位和VSS電源線間使用閘極接地之N型金氧半場效電晶體(gate-grounded NMOS, GGNMOS)。在本論文中，為了達成靜電放電防護元件能承受更大的電流及高效率的使用面積之目的，在布局上使用多指狀(multi-finger)結構，而在GGNMOS中由於寄生的BJT之電流增益(beta gain )較大而導致驟回效應(snapback)明顯而造成先導通的指根上會先燒毀之不均勻導通現象，所以，增加通道寬度並沒有使NMOS的靜電耐受度呈線性上升，為了改善此情況，本論文中在每根指頭的源極(source)插入pickup使每根指狀結構的寄生BJT的基底(base)之電阻值相同，然而，由於相較於沒有加入pickup的寄生BJT之基底電阻較小以致不容易被導通(turn-on) ，因此，其靜電耐受度下降;另外，晶片驗證結果發現GDPMOS無論是加大通道寬度或者在源極插入pickup，其靜電耐受度皆維持在很低的值，因此在第四章中提出一個新穎的結構提高以PMOS為基底的靜電放電防護元件之靜電耐受度。以上研究在28奈米的高介電係數/金屬閘極製程下實現。 在第四章中提出了一個PMOS鑲嵌在傳統的矽控整流器(Silicon-Controlled Rectifier, SCR)中之結構，其使用了CMOS標準製造過程中，為了降低觸發電壓(trigger voltage, Vt1)會加在NMOS之汲極(drain)加入P型的靜電放電佈植(P-ESD Implant)，所以不需要額外的光罩及花費，另外，相較於GDPMOS以及GGNMOS，此結構擁有單位面積下靜電耐受度較高，其中靜電耐受度包括人體靜電放電模型(Human-Body Model, HBM)及元件充電模型(Charged-Device Model, CDM)、均勻導通、寄生電容較小之特性，以及可免於栓鎖效應(latch-up)的危險等優點，因此，此設計非常適合使用在製造成本越來越昂貴、閘極氧化層厚度越來越薄以及操作電壓越來越低的先進製程中作為靜電放電防護的元件。此設計成功在28奈米的高介電係數 /金屬閘極製程下實現。

With the on-going shrinking of CMOS technologies, the devices in the integrated circuits (ICs) have been fabricated with ultra-thin gate oxide thickness to attain high speed and low power consumption. However, electrostatic discharge (ESD) events were not scaled down with the scaling in CMOS technologies. Although the high-k dielectric has been introduced in sub-50-nm CMOS technologies, the MOS transistors are still sensitive to ESD. Therefore, ESD has become the major concern of reliability for ICs in nanoscale CMOS technology. To discharge the high ESD energy without causing damage to integrated circuits, the turn-on behavior of parasitic bipolar junction transistors (BJTs) inherent in NMOS or PMOS transistors plays an important role. The NMOS and the PMOS with gate connected to source have been used as the ESD clamp devices, that is to say, gate-grounded NMOS (GGNMOS) and gate-VDD PMOS (GDPMOS). In order to discharge more ESD current and use area efficiently, the transistors utilize the multi-finger structure. The GGNMOS has obvious snapback phenomenon due to large current gain of parasitic NPN BJT. The first turn-on finger will be burn out and results in nun-uniform turn-on issue. Thus, the ESD robustness is not increasing with enlarging the width of ESD devices. In this work, inserting inner pickups in source side of MOS transistors is to improve ESD level. Measurement results indicate that additional pickups decrease the ESD robustness of the NMOS transistors because the base resistor value becomes smaller. Then, the ESD robustness of PMOS transistors almost keeps the same value whether raising the width of channel or inserting inner pickups into source side. The above statement is discussed in Chapter 2. With a view to improve the ESD performance of PMOS-based ESD clamp devices. A novel ESD protection design is proposed in and is presented in chapter 3. In chapter 3, a novel ESD protection design by using PMOS device with embedded silicon-controlled rectifier (SCR) is proposed in this work. This design employs the P-ESD implant which is put in the drain side of NMOS to lower the trigger voltage in a standard step of CMOS process. Hence, there is no need for extra mask/cost. Besides, the proposed device has the higher ESD robustness per area, more uniform turn-on behavior, and lower parasitic capacitance than GGNMOS and GDPMOS. Additionally, the proposed device has been tested to be free from latchup event. Accordingly, the proposed device can be a better solution for ESD protection in sub-50-nm CMOS process that cost becomes more expensive, the gate oxide thickness is getting to thinner, and the supply voltage is becoming lower. The above works in chapter 3 and chapter 4 have been designed, fabricated, and characterized in a 28-nm high-k/metal gate CMOS process.