標題: | 嵌入式系統草稿記憶體之程式階段感知節能管理 Phase-aware Scratchpad Memory Management for Saving Energy of Embedded Systems |
作者: | 李佳駿 Li, Chia-Chun 曹孝櫟 Tsao, Shiao-Li 資訊科學與工程研究所 |
關鍵字: | 草稿記憶體;動態管理;程式階段;嵌入式系統;節能;Scratchpad memory;dynamic management;phase;embedded system;energy saving |
公開日期: | 2014 |
摘要: | 草稿記憶體(scratchpad memory)現今被廣泛的使用在嵌入式系統中央處理器中。在效能與耗能上,草稿記憶體表現得比快取記憶體更加,因此常作為快取記憶體的替代品。靜態的草稿記憶體配置技術將最常使用的內容置放於草稿記憶體內,執行期間不更動草稿記憶體的內容,是一個簡單且有效率的方式。然而對於擁有多個熱點的複雜程式,靜態配置技術常會使得草稿記憶體空間的使用率不佳,因此動態管理技術透過在執行期間可以自由更動草稿記憶體內容的方式改善靜態配置技術的缺點。不過在真實世界中,較大型的應用程式,例如多媒體解碼器,經常有明確的程式階段行為(phase behavior),在不同的程式階段間,其程式物件的重要性將會有重大的改變,因此以往動態管理技術對於程式物件使用固定的分類將使得草稿記憶體的使用率低下。在這篇研究中,我們結合階段特性與動態管理技術,提出一個啟發式方法(heuristic approach),分出程式不同的程式階段並且為各階段的程式物件分類,另外我們也提出一個提升的架構減少轉譯後備緩衝區系統(TLBs system)的耗能。
使用我們的架構,最多可以節省93.9%的能量延遲乘積(energy delay product),平均也可以節省26.3%,而使用我們提出之分階段與分類方法,更可以比不分階段多節省5.5%的能量延遲乘積。 Scratchpad memory (SPM) is wildly used in embedded system CPU. SPM often serves as a better alternative than the hardware cache in terms of performance and energy efficiency. Static allocation techniques lock the most frequently executed parts in the SPM, do not alter the content, and are simple and effective approaches. However, for complex applications with numerous hotspots, static allocation techniques usually lead to underutilization of the SPM space. Dynamic SPM allocation techniques remedy the shortcoming by allowing the freedom of altering the SPM composition at runtime. However, for large real applications such as multimedia codecs exhibiting clear phase behavior, the importance of the code object may vary significantly in different phases indicating inflexibility of fixed classification and lower SPM utilization. Therefore, in this study, we incorporate phase classification techniques in dynamic SPM management. For energy saving, we present a heuristic approach to divide phases and classify the code objects, and we also present an improved architecture to reduce the energy consumption of TLBs system. Our architecture can reduce up to 93.9% of the energy delay product (EDP) compared to the state-of-the-art architecture, and 26.3% in average. If applications have clear phase behaviors, we can more improve up to 5.5% in energy delay product (EDP) compared to without phase division and classification method. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT070156057 http://hdl.handle.net/11536/76450 |
顯示於類別: | 畢業論文 |