適用於多天線系統之幾何平均值分解處理器

Abstract

多輸入多輸出系統中，假設傳輸端預先獲得通道資訊，即可透過預編碼的技術以波束成型抑制通道干擾。在現今的預編碼設計當中，幾何平均值分解可以將通道拆解為多組相同SNR的子通道，此特性有助於降低功率分配及比特預加載所需硬體之複雜度。本篇論文提出一個幾何平均值分解處理器，並兼備空間資訊回傳功能。此處理器適應於多維度矩陣之幾何平均值分解，此外，基於複數QR分解前處理，有效的降低硬體複雜度。需要回傳的資料量更能透過此處理器的空間資訊回傳而降低。硬體設計規格參考以WLAN IEEE 802.11ac OFDM SIFs 16 us 為標準。本篇論文所提出的幾何平均值分解處理器以90 nm CMOS實現2至8空間串流之通道分解。實現面積為1.830x1.829 mm^2, 邏輯閘數為437.7K。在操作功率於66.67MHz以及供給電壓1V之下消耗功率於為125.5mW。本篇論文提出之演算法能支援任意矩陣維度之幾何平均值分解，該硬體實現與以往的論文相較，以相似的面積與功率更兼備空間串連回送的機制。

The precoding technique can be used as beamforming to suppress cross-channel interference for multi-input multi-output (MIMO) systems if the channel state information (CSI) is known at both the transmitter and receiver. Among the current precoding schemes, Geometric-Mean-Decomposition (GMD) facilitates design of modulation and coding schemes when transmitted power is evenly allocated and bit-loading is used for all subchannels. This paper presents a flexible GMD processor that supports spatial information feedback. An efficient GMD algorithm for arbitrary-size matrices is proposed. A complex-valued bidiagonal QR decomposition is adopted as the preprocessing of GMD to reduce the hardware complexity. An efficient feedback method and associated hardware is proposed to reduce the volume of feedback information. The latency constraint for WLAN IEEE 802.11ac standard in the 16 us is used as design specification. The proposed GMD processor is design and implemented for 2 to 8 spatial streams in a 90nm CMOS technology. The chip integrates 437.7K gates in 1.830x1.829 mm^2. It dissipates 125.5mW at 66.67MHz from a 1V supply. Compared to prior work, this work supports GMD for a larger matrix, despite the added spatial information feedback capability, with comparable silicon area and power consumption.