低功耗CMOS超寬頻與毫米波低雜訊放大器之分析與設計

Abstract

本論文中，利用了0.18um 及 90nm 兩個製程設計以建立低功率的低雜訊放大器（LNA），分別應用在極寬頻(UWB)和毫微米波(millimeter)無線接收器。主要用了三種不同的電路架構去設計出電路晶片；包含了兩個UWB低雜訊放大器和1個V頻段低雜訊放大器。 第一顆UWB LNA為使用了2級的Cascade架構並且使用了電阻的並聯-並聯(shunt-shunt) 回授設計出寬頻的輸入匹配、且採用了順向基極偏壓達到低電壓和低功耗，功率增益的部份採用了級間串聯LC諧振（Inter-stage series LC resonator)使交流電流和功率增益得到有效的放大，再利用Inductive shunt peaking使得功率增益的頻寬可以延伸。我們在此電路中做了一些分析，包括輸入匹配 (S11)、輸出匹配 (S22)、功率增益(S21) 和雜訊響應 (Noise figure)；我們使用等效的小訊號分析模型可以先預測電路效能並與ADS模擬結果比較，可以使電路設計上更為快速且容易優化參數。量測數據顯示，利用此cascade結構可以有效的降低VDD，低功耗，較高的線性度（IIP3），和不錯的雜訊響應。最後量測中得到的功率增益頻寬有降低，主因為電阻Rfb在佈局上的錯誤導致過大阻值，如能更改佈局並再下線製作晶片，可以得到更符合模擬的結果。 第三顆為應用在V頻段的低雜訊放大器，一樣採用tsmc 90 nm low power RF CMOS process設計並製作晶片，此電路主要採用了三級的共源極放大器和源極退化，輸入匹配中使用傳輸線（TML）去實現，並在此使用Ansoft HFSS模擬傳輸線的效應和利用ADS建立傳輸線模型，以期在之後能更方便及快速的做電路模擬和優化。量測數據顯示，測得的功率增益較模擬的功率增益較好且>10dB，在頻帶保持不錯的輸入匹配，主要缺點為較差的雜訊響應，必須在之後的設計上主要針對此點去做更多的優化與設計。

In this thesis, low power low noise amplifier (LNA) design and fabrication have been accomplished using 0.18 m and 90 nm RF CMOS processes, for potential applications in ultra-wide band (UWB) and millimeter wave wireless receivers. The primary achievements contain three circuit chips, such as two UWB LNA and one V-band LNA, employing different circuit topologies. The first UWB LNA was built with a two-stage cascade topology, incorporating resistive shunt-shunt feedback for wideband input matching, forward body-biasing (FBB) scheme for low voltage and low power, inter-stage series LC resonator for ac current amplification and power gain boost, and inductive shunt peaking technique for bandwidth extension. An extensive work of equivalent circuit analysis has been conducted for input and output matching, power gain, and high frequency noise in UWB LNA design. Analytical models can be derived to simulate the performance parameters, such as input and output return loss, S11 and S22, power gain S21, and noise figure, responsible for the key features of major concern in UWB LNA design. The accuracy of our analytical model was justified by a good match with ADS simulation. Note that, the derived analytical model in an explicit form containing physical parameters, without need of numerical solver, can facilitate the simulation efficiency and guide the performance optimization or diagnosis. A performance benchmark indicates that this UWB LNA using a cascade topology, demonstrates the advantage of much lower VDD, lower power dissipation, higher linearity (IIP3) and comparable noise figure, but the drawback of lower S21 at higher frequency and reduced bandwidth for S21 > 10dB, due to abnormally large Rfb caused by a mistake in resistors layout. A layout correction to meet the target Rfb should offer right solution to cover the performance. Finally, the third LNA chip aimed for application in V-band receiver was design and fabricated in tsmc 90nm low power RF CMOS. This V-band LNA was implemented by a distributed amplifier containing 3-stage CS amplifiers, with inductive source degeneration at the first stage, inter-stage transmission lines (TML) for broadband matching, without need of spiral inductors, and again FBB technique for low voltage and low power. An extensive simulation has been conducted, using 3D EM simulation like Ansoft HFSS, to realize TML design aimed for V-band operation. Afterwards, the S-parameters achieved from HFSS were adopted as the design target for ADS to build TML model, which can facilitate circuit simulation and optimization. The measured chip performance indicates the advantage of higher gain S21 and wider bandwidth for S21 > 10dB than post-layout simulation. There is a shift of the minimum S11 but the input matching keeps good in required bandwidth. Higher noise appears as the primary drawback and more effort is required in the future work for an effective improvement.