在基於LLVM之二元瑪轉譯支援NEON和VFP指令集架構

Abstract

二元碼轉譯是一個用一指令集來模擬另一指令集的程序，其常被廣泛地運用在虛擬機器和模擬器上。本研究目的是在既有的以LLVM為基礎所開發的可重定目標之二元碼轉譯系統--MC2LLVM--上支援新的兩個作為客端之指令集架構NEON和VFP。本研究的二元碼轉譯系統利用LLVM的向量和浮點數運算來模擬NEON的SIMD指令和VFP的浮點數指令，充分的在前端轉譯(frontend translation)保留SIMD的平行和浮點數的本質，進而提高對主機端SIMD和浮點數處理單元的使用率。鑒於二元碼轉譯器的品質會直接的影響轉譯後的二元碼之效能，它通常需要被高度謹慎地人工優化。為了實現完全相容於NEON和VFP指令集架構，我們還必須模擬它們的架構和浮點數環境，包括清洗為零模式(flush-to-zero mode)、默認NaN模式(default NaN mode)、浮點數例外(floating-point exceptions)等等。實驗結果顯示，MC2LLVM在SPEC CPU2006的整數和浮點數程式上平均比QEMU分別快了24%和127%倍，在LINPACK上比QEMU多了2.36倍的浮點數運算的吞吐量。

Binary translation is the process of emulating one instruction set with another. The important technique is widely used in virtual machines and emulators. In this research, we extend MC2LLVM, an LLVM-based retargetable binary translation system, to support ARM NEON and VFP instruction set architectures (ISAs) as guests. The binary translation system proposed in this thesis emulates Single-Instruction-Multiple-Data (SIMD) and floating-point instructions with LLVM Intermediate Representation (IR) with vector and float types to enhance the opportunities of host SIMD and floating-point units. The quality of the translation directly impacts the perfor-mance of binary translator, so the translation is often carefully implemented. To be fully compli-ant with NEON and VFP ISAs, all the machine features have to be handled, including flush-to-zero mode, default NaN mode, floating-point exceptions, etc. The experiment results indicate that MC2LLVM is, in average, 1.24X and 2.27X faster than QEMU on the SPEC CPU2006 integer benchmarks and floating-point benchmarks, respectively, and have 3.36X more throughput of the floating-point operations than QEMU benchmarked by LINPACK.