應用於音頻訊號處理之三角積分調變器

Abstract

\hspace{0.6cm}為100dB的三角積分調變器(Delta-Sigma Moduator,DSM)設計。 三角積分轉換器(Delta-Sigma Modultaors,DSMs)因擁有高解析 度而廣為人知，常被應用在音頻訊號處理。由於電源電壓隨著CMOS製程愈來愈先進而變得愈來愈低，類比電路可用的訊號擺幅也跟著減小。 在這種條件下為了維持動態範圍，電路的熱雜訊(Thermal noise)也要跟著變小；但如此一來 功率消耗卻也變大。許多低電壓操作下，要維持動態範圍同時減低功耗的電路技巧因而產生。 例如開關運算放大器(Switched-opamp,SOP)來降低至多一半的靜態功率消耗； 使用反向器來取代傳統類比電路的運算放大器(Inverter-based)可以使電路操作在極低的 電源電壓(Low-VDD)。雙取樣(Doublesampled)技術 可以使有效時脈倍增，而使超取樣率(Over-sampling ratio,OSR)加倍。 \indent 本電路使用傳統的三角積分轉換器架構，使用切換式電容的方式實作 但仍可達到與上述電路技巧相當的結果。我們使雜訊轉移函數(Noise Transfer Function,NTF) 最佳化，以增加輸入擺幅；我們使用等效訊號的技巧來減小類比積分器的輸出擺幅。我們使用大尺寸 的電晶體以及電容，來增進電路的匹配度，同時也有效做到閃爍雜訊(flicker noise)的壓抑；因此 毋需要炫麗的電路技巧也可達到高解析度、高動態範圍的結果。 本電路設計了一個2-1疊接結構(MASH)的三角積分轉換器，其包含了一個二階的回路再 疊接一個一階的回路。操作頻率為6.25MHz，在一伏特的操作電壓下其功耗為865$\mu$W。 此電路的訊號雜訊失真比(signal-to-noise-plus-distortion ratio,SNDR)為88dB，其 訊號雜訊比(signl-to-noise ratio,SNR)為90dB，而其動態範圍(Dynamic Range,DR)為100dB。

This thesis described an audio-band Delta-Sigma Modulator(DSM), which is operated under 1~V supply.

The delta-sigma modulators (DSMs) are known for high resolution performance. They are commonly used in audio band applications. As supply voltage is scaled in CMOS technologies, the available signal swing for analog circuits is also diminished. To maintain the dynamic range, it is necessary to reduce the thermal noise of the circuit at the expense of larger power consumption. There are techniques to reduce power consumption while maintaining dynamic range under a low supply voltage. The switched-opamp (SOP) technique reduces the static power of an opamp by half \cite{Waltari01}. The inverter-based design can operate under a very low power supply voltage. The doublesampled technique can make the effective sampling as twice the clock rate, thus, doubling the over-sampling ratio. In this work, we use conventional modulator architecture and switched-capacitor circuit technique to achieve similar performance. We optimize the noise transfer function (NTF) to increase the input signal range. We scale the output range of the integrators for low-voltage operation. We use large-size MOSFETs and capacitors to improve matching and suppress flicker noise, so that fancy circuit techniques are not required. We designed a 2-1 multi-stage noise-shaping (MASH) $\Sigma \Delta$~modulator. It consists of a second-order loop followed by a first-order loop. Operating at 6.25 MHz sampling rate, it consumes 865 $\mu$W from a 1 V supply. It achieves 88 dB signal-to-noise-and-distortion ratio (SNDR), 90 dB signal-tonoise ratio (SNR), and 100 dB dynamic range(DR).