K-Band傳收器之互補式金氧半前端關鍵積體電路設計與分析

Abstract

本論文分別闡述兩個使用電流操作模式的射頻(Radio Frequency, RF)前端電路，以及使用45奈米Planar Bulk CMOS電晶體製作的低雜訊放大器(Low Noise Amplifier, LNA)，這些電路的操作頻率皆位在K頻段上。論文主要包含下列三個部分：(1)設計與分析一個操作在$K$頻段的電流操作模式(Current-Mode) CMOS接收機(Receiver)前端電路；(2)設計與分析一個操作在$K$頻段的電流操作模式CMOS傳送機(Transmitter)前端電路；(3)使用45奈米Planar Bulk CMOS之製程技術，以及Wafer-Level Package (WLP)技術所製作的高$Q$值Above-IC電感，完成設計$K$頻段之低雜訊放大器。

本論文第二章提出一個CMOS電流操作模式射頻接收機前端電路，此接收機前端電路主要由一個電流操作模式的低雜訊放大器以及一個電流操作模式的降頻混波器所組成，此接收機前端電路使用0.13-μm 1P8M CMOS製程技術實現，並可適用在24-GHz的頻段上操作。量測結果顯示此接收機的轉換增益(Conversion Gain)為11.3 dB，雜訊指數(Noise Figure，NF)為14.2dB，等效輸入端之增益1-dB壓縮點(IP-1dB)為-13.5 dBm，等效輸入端之三階互調失真點(PIIP3)為-1 dBm。 當低雜訊放大器的工作電壓使用0.8伏特，以及降頻混波器的電壓使用1.2伏特時，此接收器總共消耗27.8 mW。接收機的晶片面積為1.45 × 0.72mm2，此晶片面積包含了測試用的銲墊(Pad)。由實驗的結果分析得知，本論文所提出的電流操作模式的降頻混波器電路可以操作在K頻段，操作在低電壓下，並可達到低功率消耗的特性。此外，此一整合了電流操作模式的降頻混波器以及低雜訊放大器的接收器前端電路具有低電壓操作以及低功率消耗的特點。

本論文第三章提出一個CMOS電流操作模式射頻傳送機前端電路，此傳送機前端電路主要由一個電流操作模式的升頻混波器、一個電流操作模式的基頻(Baseband)緩衝電路、一個電壓控制震盪器，以及一個本地震盪訊號之緩衝器電路(VCO Buffer)。此傳送機前端電路使用0.13-μm 1P8M CMOS製程技術實現，並可適用在24-GHz的頻段上操作。量測結果顯示此傳送機的轉換增益為-5 dB，雜訊指數為12.7 dB，等效輸入端之增益1-dB壓縮點為-22 dBm，等校輸入端之三階互調失真點為-9.6 dBm。等效輸出端之增益1-dB壓縮(OP-1dB)點為-28 dBm，等效輸入端之三階互調失真點(POIP3)為-14.6 dBm。整合於此傳送機中的電壓控制震盪器，可提供頻率從20.8 GHz至22.7 GHz的本地震盪訊號，當電壓控制震盪器的在輸出頻率為22.7 GHz時，在10 MHz偏移頻率的條件下，其相位雜訊(Phase Nose)為-108 dBc/Hz。當工作電壓使用1伏特時，此傳送機前端電路總共消耗11.7 mW。其中，電流操作模式的升頻混撥器消耗3.1 mW，電壓控制震盪器消耗2.2 mW，本地震盪訊號之緩衝器電路消耗3.3 mW，電流操作模式的中頻放大電路消耗3.1 mW。此接收機的的晶片面積為1.5 × 1.1 mm2，此晶片面積包含了測試用的銲墊。由實驗的結果分析得知，本論文所提出的電流操作模式的升頻混波器電路可以操作在$K$頻段，操作在低電壓下，並可達到低功率消耗的特性。此外，此一整合了電降流操作模式的升頻混波器、基頻緩衝電路、電壓控制震盪器，以及本地震盪訊號之緩衝器電路的傳送器前端電路具有低電壓操作以及低功率消耗的特點。

由本論文所提出的接收器前端電路以及傳送器前端電路的實驗結果分析得知，電流操作模式的電路設計方法可運用在設計射頻積體電路，並具有低功率消耗的特點。此外，電流操作模式的電路設計方法更具有低電壓操作的特點，對於運用先進奈米CMOS製程技術來設計射頻積體電路具有相當大的潛力。

除了探討電流操作模式在射頻積體電路的可行性之外，本論文第四章分析與比較45奈米CMOS製程中之Planar Bulk以及FinFET電晶體元件之特性。並利用45奈米Planar Bulk CMOS之製程技術，以及WLP技術所製作的高Q值Above-IC電感，成功地實現兩個操作於$K$頻段之高性能低雜訊放大器。經量測驗證後，單端一級Cascode架構的低雜訊放大器的中心操作頻率為23 GHz，其增益為7.1 dB，雜訊指數為4 dB， 等效輸入端之增益1-dB壓縮點為-9.5 dBm，等效輸入端之三階互調失真點為+2.5 dBm。在工作電壓為1伏特的條件下，功率消耗為3.6 mW。此單端一級Cascode架構的低雜訊放大器的晶片面積為0.72 × 1.12 mm2，此晶片面積包含了測試用的銲墊。除此之外，單端兩級串接的Cascode架構的低雜訊放大器的中心操作頻率為23.4 GHz，其增益為11.6 dB，雜訊指數為4.4 dB，等效輸入端之增益1-dB壓縮點為-16 dBm，等效輸入端之三階互調失真點為-4.2 dBm。在工作電壓為1伏特的條件下，功率消耗為9.3 mW。此單端兩級串接的Cascode架構的低雜訊放大器的晶片面積為1.28 × 1.12 mm2，此晶片面積包含了測試用的銲墊。

本章所提出的兩個低雜訊放大器，為第一個成功的使用45奈米Planar Bulk CMOS製程，實現操作於$K$頻段的低雜訊放大器；此外，透過使用Figure-of-Merit (FOM)進行綜合效能評比，與已發表的操作在相同頻率的CMOS低雜訊放大器相互比較後，所設計的單端一級Cascode架構的低雜訊放大器，為當前性能最佳的低雜訊放大器，其FOM值可達到15.2 GHz。

In this dissertation, two radio-frequency (RF) front-end circuits using current-mode design methdologies have been proposed and implemented. Moreover, two low-noise amplifier (LNA) using 45-nm planar bulk-CMOS technology have also been implemented. The operation frequency of the two current-mode RF front-end circuits and the two 45-nm LNAs are within the frequency of K-Band. This dissertation can be mainly divided into three parts, including (1) design and analysis of the K-Band current-mode CMOS receiver front-end circuits, (2) design and analysis of the K-Band current-mode CMOS transmitter front-end circuits, and (3) The K-Band LNAs using 45-nm planar bulk-CMOS technology with high-Q above-IC inductors implemented through wafer-level package (WLP) technology.

A CMOS current-mode receiver front-end integrated circuit has been proposed. The proposed current-mode receiver front-end is composed of a current-mode LNA and a current-mode down-conversion mixer. This receiver front-end is fabricated in 0.13-μm 1P8M CMOS technology and is operated in the frequency band of 24 GHz. From the measurement results, the proposed integrated current-mode receiver front-end has the conversion gain of 11.3 dB, the input-referred 1-dB compression point (IP–1dB) of –13.5 dBm, and the input-referred third-order intercept point (PIIP3) of –1 dBm. The measured noise figure (NF) is 14.2 dB at the RF frequency of 24 GHz and LO frequency of 19 GHz. The total power dissipation of this current-mode receiver front-end dissipates 27.8 mW under the condition that the supply voltage of LNA is 0.8 V and the supply voltage of mixer is 1.2 V. The proposed current-mode receiver front-end occupies the active area of 1.45 × 0.72 mm2 where testing pads are included. From the experimental results, the proposed CMOS current-mode down-conversion mixer can operate well in the K-band, and achieves low-power consumption under low power supply voltage. It can also be shown that the proposed receiver front-end circuit that is integrated with a current-mode down-conversion and LNA has the advantage of low-voltage operation and low-power consumption.

A CMOS current-mode transmitter front-end integrated circuit has been proposed. The proposed current-mode transmitter front-end is composed of a current-mode upconversion mixer, a current-mode baseband amplifier/repeater, a VCO and a transformerbased VCO buffr/repeater. This transmitter front-end is fabricated in 0.13-μm 1P8M CMOS technology and is operated in the frequency band of 24 GHz. The measured results have shown that the proposed integrated current-mode transmitter front-end exhibits a measured conversion power gain of –5 dB, an IP-1dB of –22 dBm, an output-referred 1-dB compression point (OP-1dB) of –28 dBm, PIIP3 of –9.6 dBm, and an output-referred third-order intercept point (POIP3) of –14.6 dBm. The single-sideband (SSB) noise figure (NF) is about 12.7 dB. The on-chip VCO provides the LO frequency from 20.8 GHz to 22.7 GHz with the control voltage varied from 0 V to 2 V. The phase-noise of the VCO is -108 dBc/Hz at 10-MHz offset from 22.7 GHz. Under the 1-V supply voltage, the fabricated current-mode double-balanced up-conversion mixer, VCO, VCO buffer/repeater and baseband current buffer/repeater circuits dissipate 3.1 mW, 2.2 mW, 3.3 mW, and 3.1 mW, respectively. The proposed transmitter front-end occupies the active area of 1.5 × 1.1 mm2 where testing pads are included. From the experimental results, the proposed CMOS current-mode up-conversion mixer can operate well in the K-band, and has a very small power consumption. Moreover, it can also be sown that the proposed transmitter front-end circuit that is integrated with a current-mode up-conversion mixer, a baseband current buffer/repeater, a VCO, and a transformer-based VCO buffer/repeater has the advantage of low-voltage operation and low-power consumption.

From the experimental results of the proposed receiver front-end and transmitter frontend circuits, it can be shown that the current-mode design approach is suitable for designing RF integrated circuits and has the advantage of low-power consumption. Moreover, the current-mode approach also has the advantage of low-voltage operation and has great potential for designing RF integrated circuits in advanced nanometer CMOS technologies.

In addition to investigating current-mode approach to the RF integrated circuits, two K-band high performance LNAs have been successfully realized by using the 45-nm planar bulk-CMOS technology and high-Q above-IC inductors in WLP technology. The first LNA is made up of a single-ended one-stage cascode amplifier. The measurement results of the implemented one-stage cascode LNA show that the one-stage LNA has a NF of 4 dB, a gain of 7.1 dB, an IP-1dB of –9.5 dBm, and a PIIP3 of +2.25 dBm. The center frequency of this LNA is about 23 GHz. The LNA consumes 3.6 mW from 1-V power supply voltage. The one-stage cascode LNA occupies the active area of 0.72 × 1.12 mm2. Moreover, the measurement results of the implemented two-stage cascaded cascode LNA show that the two-stage LNA has a NF of 4.4 dB, a gain of 11.6 dB, an IP-1dB of –16 dBm, and a PIIP3 of –4.2 dBm. The center frequency of the two-stage LNA is about 23.4 GHz. The LNA dissipates 9.3 mW from 1-V power supply voltage. The two-stage cascaded cascode LNA occupies the active area of 1.28 × 1.12 mm2.

It is at present the first two successfully verified 45-nm planar bulk-CMOS LNAs operated above 10 GHz. Moreover, as compared to prior works which are operated at the frequency around K-band, it has been shown that the proposed one-stage cascode LNA has the best performance in terms of figure-of-merit (FOM). The FOM of the proposed one-stage cascode LNA is 15.2 GHz.