內嵌式金屬編碼唯讀記憶體之雜訊處理技術

Abstract

在系統單晶片(SoC)上,由於模式的變化,易引起雜訊的起伏而造成模式敏感的軟錯誤。此模式敏感的軟錯誤對於內嵌式金屬編碼唯讀記憶體(ROM)和其他系統單晶片上的敏感電路變得越來越重要。內嵌式金屬編碼唯讀記憶體在系統單晶片(SoC)上是雜訊的受害者亦是加害者。本論文針對唯讀記憶體中由於雜訊和模式敏感引起的功能失敗作深入的分析研究。並且針對內嵌式金屬編碼唯讀記憶體提出了創新技術以克服雜訊和模式敏感所引起的功能失敗。此外,本論文亦針對由於內嵌式金屬編碼唯讀記憶體所引起的電源雜訊的起伏與金屬編碼唯讀記憶體讀取模式之倚賴性作深入的研究,並且提出了新技術以減少系統單晶片上電源雜訊的起伏。 位元線之間的耦合雜訊干擾易引起高速內嵌式金屬編碼唯讀記憶體的讀取失敗以及限制其可適用的碼模式(code-pattern)。由於金屬編碼唯讀記憶體之每一位元線上的寄生電容量會依其碼模式不同而不同,每一位元線遭受的耦合雜訊量亦會依其碼模式不同而不同。本文針對內嵌式金屬編碼唯讀記憶體提出動態虛擬保護(DVG)技術,以消除位元線之間之耦合雜訊所引起之讀取失敗的問題，並且提供NOR型高速金屬編碼唯讀記憶體100%的碼型態覆蓋範圍。與傳統唯讀記憶體比較,DVG技術可達到更高速度,更低的功率消耗和更好的DFM能力。本文使用0.25微米以及0.18微米CMOS製程驗證DVG技術。 當晶片上的地線雜訊和基體雜訊因為不同執行模式而引起大的起伏,晶片上的內嵌式唯讀記憶體遭受到雜訊干擾而易引起功能失敗。本文針對內嵌式唯讀記憶體提出一個雜訊追蹤過濾(NTAF)的架構,以克服因為接地線雜訊和基體雜訊的起伏而引起唯讀記憶體的功能失敗。此NTAF的架構有二種追蹤方法,一為分享式追蹤串(STC),另一方法為動態式追蹤串(DTC)。NTAF,它是具有專門布局模式的自我時序控制的電路,以提供因為雜訊需要的時序鬆弛,並且減少非必要的速度延遲。 在使這個速度退化減到最少時。NTAF提供更大的雜訊容忍度和設計為製造(DFM) 能力。因此NTAF可提供內嵌式唯讀記憶體更大的雜訊容忍度和設計為製造(DFM)的能力。此設計使用0.18微米CMOS製程。 由於晶片在不同週期和模式上電流消耗不同,此電流消耗的變化會引起晶片上電源雜訊的起伏,進而引起晶片功能退化以及模式敏感的軟錯誤。非常遺憾,在金屬編碼唯讀記憶體上不同的碼模式會造成大的電流消耗變化以及大的電源雜訊的起伏。為了降低因為電流消耗的變化而引起電源雜訊的起伏,本文針對內嵌式金屬編碼唯讀記憶體提出一混合內容敏感的架構(HSCSA)以及一內容意識的設計框架(CADF)。HSCSA技術可以有效地減少金屬編碼唯讀記憶體的電流消耗之最大峰值以及達到更低的功率消耗,並且適用於各種代碼模式和週期。CADF技術除了可減少電流消耗值和電流最大峰值,亦可避免耦合雜訊而引起的功能失敗。本文使用0.25微米CMOS製程驗證CSA和CADF技術。 總之,本文針對系統單晶片(SoC)上內嵌式唯讀記憶體之內部和外部的雜訊(雜訊的受害者),以及影響其他電路的雜訊(雜訊的加害者)提出了數種有效創新的雜訊處理技術。

Pattern-sensitive soft errors, subject to fluctuations of on-chip noises, have become increasingly significant for embedded read only memories (ROMs) and other sensitive blocks in system-on-a-chip (SoC). In this dissertation, the noise-induced and pattern-sensitive failures of contact/via-programmed ROMs are investigated. Techniques to overcome the pattern-sensitive failures of contact/via-programmed ROMs are proposed. Furthermore, the pattern-dependent fluctuation of supply noise induced by embedded ROMs is also studied and reduced. Crosstalk between bitlines induces read failure and limits the coverage of applicable code-patterns for high-speed contact/via-programming ROMs in SoC. Owing to the variation in bitline loading across code-patterns, the amount of coupled noise on an accessed bitline is code-pattern-dependent. The dynamic virtual guardian (DVG) techniques are proposed for contact/via-programming ROM macros and compilers to eliminate the crosstalk-induced read failure and increase the code-patterns coverage. Compared with conventional ROMs, DVG techniques achieve higher speed, lower power consumption and better design for manufacturing (DFM) capability with full code-patterns coverage. Experiments on fabricated designs with 0.25µm and 0.18µm CMOS technologies have demonstrated that DVG techniques can achieve 100% code-pattern coverage under a small sensing margin for various technology nodes. When subject to various operational patterns, large on-chip or internal ground noise and substrate noise occur in a SoC. Configurable embedded ROMs are importantly affected with pattern-dependant failures induced by noises. A noise track-and-filter (NTAF) architecture with two tracking column schemes are proposed to tolerance the ground noise and substrate noise. The two tracking schemes include the shared tracking cluster (STC) and dynamic tracking cluster (DTC). The NTAF, which are self-timed circuits with specific layout patterns, are presented to provide the required timing relaxation, while minimizing the speed degradation. The NTAF provides greater noise tolerance and DFM capability. Configurable embedded ROMs in 0.18µm CMOS process are studied. Supply noise and its variations, caused by fluctuations of on-chip currents across cycles and patterns, leads to performance degradations or pattern-dependent functional failures for SoC designs. Unfortunately, various code-patterns of contact/via-programming ROMs cause significant fluctuations in current consumptions and supply noise. Hybrid-structured content-sensitive architecture (HSCSA) and content-aware design framework (CADF) for embedded contact/via-programmed ROMs are presented to reduce the fluctuation of supply noise. The HSCSA ROM effectively reduce the fluctuation of peak current and lower the power consumption of ROMs for various code-patterns and running cycles. The CADF ROM that effectively 1) reduces both fluctuations of peak current and cycle current for various code-patterns and cycles, and 2) avoids the crosstalk induced read failure. Experiments on HSCAS ROMs and a CADF ROM using 0.25µm CMOS technology had demonstrated that fluctuation of peak current and power consumption were significantly reduced compared to the conventional approach. In summary, several pattern-insensitive techniques are proposed to deal with the internal/external noises for embedded contact/via-programmed ROM in this dissertation.