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dc.contributor.authorLi, Katherine Shu-Minen_US
dc.contributor.authorLee, Chung-Lenen_US
dc.contributor.authorSu, Chauchinen_US
dc.contributor.authorChen, Jwu E.en_US
dc.date.accessioned2014-12-08T15:10:05Z-
dc.date.available2014-12-08T15:10:05Z-
dc.date.issued2009-02-01en_US
dc.identifier.issn1063-8210en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TVLSI.2008.2004548en_US
dc.identifier.urihttp://hdl.handle.net/11536/7696-
dc.description.abstractFor very deep sub-micrometer VLSI, crosstalk becomes an important issue in affecting performance and signal integrity of the circuits. Two crosstalk fault effects, namely, glitch and crosstalk-induced delay, in the system-on-chip (SOC) interconnect bus are analyzed and a unified scheme to detect them is proposed and demonstrated in this paper. The crosstalk induced delay is found to be superposition of the induced glitch and the applied signal at the victim line, and this effect is more important in affecting the circuit performance. A pulse detector with an adjustable detection threshold is proposed to detect glitches and consequently the induced delay. Several issues affecting the yield of the proposed testing scheme are discussed and Monte Carlo simulations are conducted to show the feasibility of the scheme.en_US
dc.language.isoen_USen_US
dc.subjectCrosstalken_US
dc.subjectdelayen_US
dc.subjectglitchen_US
dc.subjectinterconnecten_US
dc.titleA Unified Detection Scheme for Crosstalk Effects in Interconnection Busen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TVLSI.2008.2004548en_US
dc.identifier.journalIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMSen_US
dc.citation.volume17en_US
dc.citation.issue2en_US
dc.citation.spage306en_US
dc.citation.epage311en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000262778500014-
dc.citation.woscount5-
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