完整後設資料紀錄
DC 欄位語言
dc.contributor.authorLee, Ko-Huien_US
dc.contributor.authorHsu, Hsing-Huien_US
dc.contributor.authorLin, Horng-Chihen_US
dc.contributor.authorHuang, Tiao-Yuanen_US
dc.date.accessioned2014-12-08T15:10:06Z-
dc.date.available2014-12-08T15:10:06Z-
dc.date.issued2009-02-01en_US
dc.identifier.issn0021-4922en_US
dc.identifier.urihttp://dx.doi.org/10.1143/JJAP.48.021203en_US
dc.identifier.urihttp://hdl.handle.net/11536/7715-
dc.description.abstractIn this work, a novel polycrystalline silicon (poly-Si) nanowire thin-film transistor (NW-TFT) with side-gated configuration and a high-k material capping was fabricated and characterized. It was found that the gate fringing field effect via the high-k passivation layer can effectively improve the device performance in terms of higher ON current, larger ON/OFF current ratio, and steeper subthreshold slope (SS). The drain-induced barrier lowering (DIBL) effect is also effectively suppressed owing to better gate control. (C) 2009 The Japan Society of Applied Physicsen_US
dc.language.isoen_USen_US
dc.titlePerformance Improvement of Polycrystalline Silicon Nanowire Thin-Film Transistors by a High-k Capping Layeren_US
dc.typeArticleen_US
dc.identifier.doi10.1143/JJAP.48.021203en_US
dc.identifier.journalJAPANESE JOURNAL OF APPLIED PHYSICSen_US
dc.citation.volume48en_US
dc.citation.issue2en_US
dc.citation.epageen_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000264955900033-
dc.citation.woscount0-
顯示於類別:期刊論文


文件中的檔案:

  1. 000264955900033.pdf

若為 zip 檔案,請下載檔案解壓縮後,用瀏覽器開啟資料夾中的 index.html 瀏覽全文。