掃描串列故障診斷的新手法

Abstract

隨著半導體製程的不斷演進，和電腦輔助設計工具(EDA)的持續發展，使得現今的數位積體電路設計可以在有限的矽晶圓面積容納更多的功能，然而動輒百萬的邏輯閘也加重了晶片測試的困難度，因此可測試性設計(DFT)也就廣氾受到眾多數位設計工程師的注意,透過適度掃描串列(SCAN CHAIN)的設計，可大幅降低複雜晶片測試上的困難，然而隨著邏輯閘的不斷增加，這些掃描串列結構佔全部晶片面積的比重也持續上升，因此這些串列結構能否正常工作也將影響晶片測試的最終良率(Yield)，所以需要發展一些機制來找出無法正常運作的掃描串列結構•在先前的機制發展中，Stuck-At 錯誤模型是發展最成熟，也是最廣為人知的一個模型，但在深次微米的先進製程及高速晶片操作的要求下，舊有錯誤模型已難以解釋新產生的問題，所以又有一些新的錯誤模型被發展出來，諸如暫態模型，路徑延遲模型，橋接模型(Bridging)，資料保持模型(Hold-Time) 等等，在過去的文獻資料中，資料保持模型較少被討論，因此本篇論文將探討資料保持模型的錯誤診斷，並提出一種貪婪(Greedy)的錯誤診斷機制來找出無法正常運作的掃描串列結構，此外該機制也可在非理想的環境中擁有不錯的診斷結果 •

As the continuing improvement on the semiconductor process technology and EDA (Electronic Design Automation) industry, it allows the current digital IC design to put more functions within the limited silicon die area. However, a million-gate- count design makes the chip testing become more difficult , so DFT(Design for Testability) has gained a lot of popularity recently. The use of the scan chain structure can lower down the difficulty in testing and/or diagnosing complex chips, as the gate count grows, the overhead of scan chains increases accordingly as well. Thus, whether these scan chains function correctly or not will affect the final yield of the chip. Therefore, some mechanisms are needed in order to find out the faulty scan chains if necessary. In the literature, the stuck-at fault is the most popular fault model. For today’s DSM (deep sub-micron) or even nanometer designs, however, this traditional stuck-at fault model is often not adequate when it comes to the fault diagnosis. Other more realistic fault models have been in use, such as the transition fault model (slow to rise, slow to fall), the path delay fault model, the bridge fault model, and the hold- time violation fault model, etc. In the past, the hold-time violation fault model is rarely discussed. But today, it occurs more often and has been one of the main targets in scan chain diagnosis. This thesis will particularly focus on this type of fault model. We propose a new greedy algorithm to explore the faulty flip-flops in the scan chains. As compared to the previous methods, this algorithm is particularly robust and able to identify the fault with a higher success rate, even under some non-ideal situations, e.g., when there are multiple hold-time faults in the scan chain, when the core logic is also faulty, or when the hold-time faults are intermittent.