九十奈米深溝製程動態隨機存取記憶體位元線接觸窗失效模式之研究

Abstract

本論文主要的研究對象是九十奈米深溝製程動態隨機存取記憶體位元線接觸窗(Bitline Contact)，此接觸窗與深溝電容的接觸良好與否，對於晶圓的良率影響甚鉅。在這個研究中，吾人從數種可能的失效模式中，利用實驗設計法 (Design of Experiment )，設計出五種單因子隨機實驗(閘極間隔條厚度、閘極關鍵尺寸、氮化鈦襯裡的厚度、單側淺溝絕緣的蝕刻時間、深溝關鍵尺寸)，並利用變異數與迴歸分析等統計學理論，來推導出最佳的製程參數組合。最後得到：深溝關鍵尺寸和閘極關鍵尺寸是影響DRAM位元線接觸窗的主要製程參數，其他3個參數不具統計上的顯著性。另外，並將迴歸式所得之結果與生產線上最佳良率晶圓之SEM量測值相互印證，證實了本論文實驗方式與結果之正確性。本研究所提之失效分析模式可快速應用到生產線上，進而提高晶圓良率，增加晶粒之產出，並提供半導體業界發展位元線接觸窗接觸改善上之參考。

The main topic of this research is Bit-Line Contact for 90 nm Deep Trench DRAM. The condition of Bit-Line contact influences yield of wafers enormously. In the study, we chose DOE (Design of Experiment) to organize the experiment. Five parameters, namely GC spacer thickness, GC critical dimension, TiN liner thickness, SSBS etching time and DT critical dimension were selected as the major factors. The statistical theory such as ANOVA and Regression analysis were implemented to calculate the best process window setting. From the statistical result, we figure out the DT CD and GC CD were the most significant factors which affected Bit-Line contact conditions. The other parameters were with minor significance. The SEM observation of the best yielding wafer showed that the results of the proposed regression function were in accordance to the experiments. The analysis method could be implemented to production line for yield improvement and better chips output. Moreover, the failure analysis mode could be used in other semiconductor enterprises for the improvement of the Bit-Line contact related issues.