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dc.contributor.authorLu, Hungwenen_US
dc.contributor.authorSu, Chauchinen_US
dc.contributor.authorLiu, Chien-Nan Jimmyen_US
dc.date.accessioned2014-12-08T15:10:12Z-
dc.date.available2014-12-08T15:10:12Z-
dc.date.issued2009-01-01en_US
dc.identifier.issn1549-8328en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCSI.2008.926578en_US
dc.identifier.urihttp://hdl.handle.net/11536/7786-
dc.description.abstractThis paper proposes a tree-topology multiplexer (MUX) that employs a multiphase low-frequency clock rather than a high-frequency clock. Analysis and simulation results show g that the proposed design can achieve higher bandwidth and be less ss sensitive to process variations than the conventional single-stage MUX. In order to verify the feasibility, this proposed design is integrated with a multiphase phase-locked loop and a low-voltage differential signaling driver in a 0.18- mu m CMOS technology. Measured results indicate that the proposed design can operate tip to 7 gigabits/s under 0.3-Ul jitter limitation.en_US
dc.language.isoen_USen_US
dc.subjectI/Oen_US
dc.subjectmultiplexeren_US
dc.subjectMUXen_US
dc.subjectserdesen_US
dc.subjectserializeren_US
dc.titleA Tree-Topology Multiplexer for Multiphase Clock Systemen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TCSI.2008.926578en_US
dc.identifier.journalIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERSen_US
dc.citation.volume56en_US
dc.citation.issue1en_US
dc.citation.spage124en_US
dc.citation.epage131en_US
dc.contributor.department電控工程研究所zh_TW
dc.contributor.departmentInstitute of Electrical and Control Engineeringen_US
dc.identifier.wosnumberWOS:000263297800012-
dc.citation.woscount6-
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