先進互補式金氧半電晶體及氮化矽快閃式記憶元件之可靠度分析和蒙地卡羅模擬

Abstract

本篇論文主要著重在蒙地卡羅模擬(Monte Carlo simulation)於先進互補式金氧半電晶體(advanced CMOS)及氮化矽快閃式記憶元件(SONOS flash memory)之應用。此外，高介電閘極氧化層(high-k)之可靠性議題，如電壓溫度引致不穩定(BTI)之研究，亦有所探討。

第一章首先描述本論文中蒙地卡羅模擬之三項應用研究成果。前兩項探討NOR型氮化矽記憶陣列中，寫入干擾(program disturb)以及電子非平衡傳輸(non-equilibrium transport)之物理機制。元件基本結構及寫入方法亦有清楚描述。最後一項應用是研究對於鍺通道(Ge-channel)雙閘極(double gate)電晶體，量子效應對電洞遷移率(hole mobility)之影響。此外，吾人於此篇論文最後，強調高介電閘極氧化層中負電壓溫度引致不穩定之重要性。

第二章探討在潛擴散式(buried diffusion)位元線SONOS陣列中，當位元線寬度變窄時所衍生之寫入干擾現象。實驗結果顯示，寫入干擾造成鄰近元件之臨界電壓有1伏特的增加，使得寫入干擾已成為50奈米NOR型SONOS 技術開發之主要問題之一。吾人採用多階式蒙地卡羅模擬來探討寫入干擾之物理機制。研究結果顯示，在熱電子寫入的過程中，鄰近元件臨界電壓會漂移的原因，是由於撞擊游離所產生之二次電子，注入至鄰近元件。此種效應對於窄位元線、淺潛擴散接面以及高摻雜環形佈值濃度之元件，將愈益明顯。此外，吾人發現透過熱電子寫入電壓以及元件結構之最佳化，可將減低寫入干擾。

第三章提出一種在潛擴散式位元線SONOS陣列中新的熱電子寫入方法。此方法是利用在奈米尺度電子呈現之非平衡傳輸現象。與傳統熱電子寫入方法不同，電子加速是在兩個相鄰元件內完成。因此，汲極至源極電壓(Vds)可降低至2.5伏特，以解決閘極長度微縮時所遭遇之貫穿(punch-through)問題。吾人亦利用蒙地卡羅模擬來探討電子非平衡傳輸行為。研究結果顯示，新的熱電子寫法方式比傳統熱電子寫入方法具有更高之寫入效率，這是因為電子經過潛擴散區域後，在寫入單元之源極端具有殘存的能量。此外，當位元線微縮時，新的熱電子寫入方法將更有效率。

第四章探討對於鍺通道雙閘極電晶體，量子效應對電洞遷移率之影響。低電場之電洞遷移率是透過蒙地卡羅方法求得。模擬結果得知，對於 (100) /[110] 「矽」通道，電洞遷移率隨著通道厚度變薄而減少。此模擬結果與實驗相符合。然而對於(100)/[100]「鍺」通道，電洞遷移率在某個通道厚度下具有最大值。此現象乃因「次能帶內」散射與「次能帶間」散射交互作用下所產生。在(110)/[-110]「鍺」通道方向上，亦可發現相同情形。此外，吾人發現當單軸壓縮應力施於(100)/[110]或(110)/[-110]鍺通道上時，電洞遷移率將可進一步提昇。

在第五章，吾人利用電腦自動化量測電路系統，研究HfSiON pMOSFETs中負電壓溫度所引致之不穩定性。實驗結果顯示，在某特定加壓條件下，負電壓溫度加壓所引致之汲極電流，將從增益模式逐漸演變成退化模式，隨著加壓時間或加壓電壓之呈現奇特的「轉彎現象」(turn around)。此外，對於pMOSFET元件加壓後，汲極電流呈現退化行為。然而，對於nMOSFET元件加壓後，汲極電流呈現恢復行為。吾人提出一「雙極電荷捕捉模型」成功解釋奇特的「轉彎現象」，並以單電荷散逸量測、電荷幫浦法以及載子分離量測，驗證所提出之物理模型。

This thesis will focus on the Monte Caro simulation and its applications to advanced CMOS and SONOS flash memory. The reliability issue, negative bias temperature instability (NBTI) in advanced gate dielectric (high-k), is studied as well.

In Chapter 1, three applications of Monte Carlo simulation are firstly addressed. The first two are the investigations of program disturb and electron non-equilibrium transport in a NOR-type SONOS array. The device configuration and program methods of the cell are described. The third application is the study of quantum confinement effects on hole mobility in Ge-channel double gate pMOSFETs. The role of NBTI in high-k gate dielectric is also emphasized.

In Chapter 2, the new program disturb in a buried diffusion bit-line SONOS array is investigated. Our characterization shows that the program disturb is 1V, which has been a major issue for the 50nm technology node and beyond. We utilize a multi-step Monte Carlo simulation to explore the disturb mechanism. We find that the threshold voltage shift of a disturbed cell is attributed to impact ionization-generated secondary electrons in a neighboring cell when it is in programming. The disturb is more serious for the small bit-line width, shallow bit-line junction, and high pocket implant dosage. In addition, we find that optimization of program bias conditions and device structure can alleviate the program disturb.

Proposed in Chapter 3 is a novel hot-electron programming method by means of electron non-equilibrium transport in a buried-diffusion bit-line SONOS memory array. In this method, electron acceleration is achieved in two adjacent cells rather than in a single cell. In this way, the drain-to-source voltage (Vds) in each cell can be reduced to 2.5V, which is immune to channel punch-through. The Monte Carlo simulation similar to that described in Chapter 2 is employed to explore the non-equilibrium transport behavior. Our study shows that the higher programming efficiency in this method than in the conventional method is attributed to the residual energy at the source of the program cell. Furthermore, this method is more effective as bit-line width reduces.

The quantum confinement effects on hole mobility in Ge-channel double gate MOSFETs are studied in Chapter 4. The low-field hole mobility is calculated by a Monte Carlo simulation. Our simulation result shows that the hole mobility in a (100)/[110] silicon well decreases with a decreasing well thickness, which is in agreement with the experimental result. The hole mobility in a Ge-channel pMOSFET, however, exhibits a peak in a sub-20 nm well because of the interplay between intrasubband and intersubband scatterings. The peak mobility in (110)/[-110] channel direction can be also achieved. Moreover, we find that the hole mobility can be further improved when the uniaxial compressive stress is applied to (100)/[110] or (110)/[-110] channel direction.

The characteristic of bipolar charge trapping induced anomalous NBTI in HfSiON gate dielectric pMOSFETs is demonstrated in Chapter 5 by using a fast transient measurement technique. Our study shows that in certain stress conditions, the NBT-induced current instability evolves from enhancement mode to degradation mode, giving rise to an anomalous turn-around characteristic with stress time and stress gate voltage. Persistent post-stress drain current degradation is found in a pMOSFET, as opposed to drain current recovery in its n-type MOSFET counterpart. A bipolar charge trapping model along with trap generation in a HfSiON gate dielectric is proposed to account for the observed phenomena. Post-stress single charge emissions from trap states in HfSiON are characterized. Charge pumping and carrier separation measurements are performed to support our model.

Conclusions are finally made in Chapter 6.