高介電係數介電質材料應用於金氧金電容之研究

Abstract

根據國際半導體技術藍圖制定會(ITRS)，元件尺寸必須不斷的縮微，為了配合現今類比、射頻通訊和記憶體元件的發展，金氧金電容(MIM Capacitor)的研發是刻不容緩的。在各種不同的被動元件中，金氧金電容經常被廣泛的應用在射頻電路裡的阻抗匹配與直流濾波器中；然而，它們通常卻占據了很大的電路面積。此外，金氧金電容也是發展高密度動態記憶體中所面臨的重要挑戰之一。因此，為了有效降低晶片的面積與節省成本，提高單位面積的電容值是極為需要的。為了達到未來記憶體元件的高電容密度要求，高介電係數介電質材料的開發似乎是唯一的選擇。當使用高介電質材料時，在增加材料的介電常數和減少元件厚度所伴隨而來的高漏電，更是目前主要的研究議題之一。 目前高介電材料應用於金氧金電容從氮氧化矽(k~4-7)、氧化鋁(k~10)、氧化鉿(k~22)、氧化鉭(k~25)，一直發展到氧化鈮(k~40)。但是目前在這些材料中還無法同時達到在高電容密度下金氧金電容所需要的特性，例如：低漏電、低電壓和低電容變化係數。因此，我們發展出新的製程和高介電係數的材料來改進金氧金電容，例如氧化鎳(k~30-40)、氧化鐠(k~26-32)和鈦酸鍶(k>50)。為了進一步改善介電質低能隙的缺點，我們利用較高功函數金屬鉑或銥當作上電極，可以得到較佳的元件特性。 雖然，鈦酸鍶具有高介電係數，但較低的導帶不連續(conduction band discontinuity)和能帶寬度(bandgap)，會造成較大的電流。鈦酸鍶必須要形成結晶相才能具有較高的介電係數(k~150-170)，而要形成奈米結晶(nano-crystal)的鈦酸鍶，則需要較高的製程溫度(>450oC)，這不適用於後段製程。此外，鈦酸鍶具有電壓電容係數(Voltage coefficient of capacitance)較高的缺點。因此，我們利用氧化鉭具有降低漏電流以及改善電壓電容係數的特性，將氧化鉭以一定比例摻入鈦酸鍶中，可有效降低整體元件的漏電流和電壓電容係數。此外，我們也成功發展出一種電漿處理(Plasma treatment)介電質的方法，不但在漏電流上有明顯的改善，也同時改良了電壓電容係數和溫度電容係數(Temperature coefficient of capacitance)。 除了基本的漏電流與低頻量測以外，我們也量測了射頻電容的高頻散射參數。並利用模擬軟體，淬取出元件在不同頻率所具有的電容大小。除此，我們還深入探討電容的傳導機制與電容變化跟電壓和溫度相關的成因，相信本篇論文對未來發展高效能金氧金電容會有很大的助益。

According to International Technology Roadmap for Semiconductor (ITRS), continuous increasing the capacitance density is required to scale down the device size and the cost of Metal-Insulator-Metal (MIM) capacitors which are widely for Analog, RF and DRAM functions. However, they often occupy a large fraction of circuit area. To meet these requirements, high dielectric constant (k) materials provide the only solution since decreasing the dielectric thickness (tk) degrades both the leakage current and ΔC/C performance. To achieve this goal, the only choice is to increase the k value of the dielectrics, which have evolved from SiON (k~4-7), Al2O3 (k=10), HfO2 (k~22), Ta2O5 (k~25) to Nb2O5 (k~40). To further achieve the properties of MIM such as low leakage current, low voltage coefficient of capacitance and low temperature coefficient of capacitance. Thus, we have developed novel process and high-k dielectric materials, such as TiNiO (k~30-40), TiPO (k~26-32) and SrTiO3 (k>50) to achieve this technology. To further improve the small bandgap (EG) of these dielectrics, we apply the higher work-function Pt (5.7 eV) and Ir (5.3 eV) top electrode are used to give better device performance. Although SrTiO3 has large dielectric (k~50-200), the small conduction band offset (ΔEc) and bandgap leading to larger leakage current is a larger drawback. Besides, SrTiO3 shows its higher k values by forming nano-crystals, which is only practicable at a higher process temperature > 450oC. Furthermore, the high voltage coefficient of capacitance of SrTiO3 is also an important issue. Because Ta2O5 has very low voltage coefficient of capacitance and can considerably suppressed the leakage current, the overall electrical characteristics of MIM device could be improved by doping Ta2O5 into SrTiO3 MIM capacitor. Otherwise, we have developed a plasma treatment on dielectric to repair the defect of the dielectric to improve leakage current, voltage coefficient of capacitance and temperature coefficient of capacitance at the same time. Therefore, not only high capacitance and low leakage current, but also small voltage/temperature dependence of capacitance are obtained under limited thermal budget for back-end-integration. In addition to the measurement of capacitance at low frequency and the leakage current, the measurement of the S-parameters to investigated the characteristics of the MIM capacitors at RF regime are also demonstrated. By using the simulation software, the capacitance density of MIM capacitors at different frequencies was extracted. Besides, the related factors such as understandings of the mechanism of conductivity, the voltage/temperature dependence of capacitances, barrier height, and interfacial layer were investigated, and these are also useful in the development of advanced MIM capacitors.