標題: H.264解碼器之資料交換層級系統模擬
Transaction Level Modeling of H.264 Decoder
作者: 陳治傑
Chih-Chieh Chen
蔣迪豪
Ti-Hao Chiang
電子研究所
關鍵字: 資料交換層級;內部預測;外部預測;H.264解碼器;TLM;intra prediction;interprediction;H.264 decoder
公開日期: 2006
摘要: 本篇論文中,我們介紹了一個在由上至下的設計流程中新的抽象層級稱之為資料交換層級。此層級主要模擬的系統架構的資料流動。因為它抽象化了需多系統層級所不需要資訊,因此它擁有較高的模擬速度。除此之外它,也可以當作系統相關軟體開發的平台,幫助提早著手進行軟體開發。在我們的研究中使用H.264解碼器當作設計範例,除了DRAM控制介面是用RTL實現,其他的所有相關模組都是以SystemC語言來撰寫。 對於個別獨立區塊的硬體設計,本篇論文針對了內部以及相互預測提供了一套硬體架構。利用在解碼的過程中一個巨塊不會同時利用到內部以及相互預測的特性,設計了一套既可以處理內部預測也可以處理相互預測單一硬體架構來增加硬體使用效率以及降低成本。對於內部預測我們使用兩次一維的過濾器來實現二維的過濾。對於內部預測,我們先將邊界點重組後在丟入過濾器中。與現有的設計方式比較,我們的設計在使用較低的成本下還能提供較好的表現。 總結,本論文證明了利用資料交換層級確實能更有效率的模擬系統層級,並且對於系統開發與評估有很大的幫助。可見資料交換層級將在未來的單一晶片系統設計時代扮演著重要的角色。同時,論文中所提出的內部以及相互預測的硬體架構相也表現出具有更好的硬體使用效率以及更低的成本的特性。
In this thesis, we introduce transaction level modeling (TLM) which is a new level of abstraction in the top-down design methodology. It mainly models the data flow of the overall system architecture. Because it ignores some details that are not important for system architecture, it can simulate faster and figure out problems about system earlier. In addition, it serves as a platform for software development in the early stage. In our study, we concentrate on H.264/AVC decoder as a pilot application. We implement the individual modules in SystemC except for the DRAM controller that is implemented in RTL. As for the hardware design of individual module, we present a unified systolic architecture for inter and intra predictions. To increase hardware utilization and minimize cost, we combine inter and intra prediction by a reprogrammable FIR filter, which is further implemented with systolic array. For inter prediction, the 2-D interpolation is conducted through separable 1-D filtering. For intra prediction, the boundary pixels are reshuffled before feeding into the systolic array. As compared with state-of-art design approaches, our architecture provides higher performance while maintaining relatively lower cost. In conclusion, this work proves that TLM can model the system more efficient and be helpful for design exploration. Thus, it will play a key role in SoC design era with more complexity. In addition, our unified systolic architecture for inter and intra predictions also shows that it has more hardware efficiency and lower cost.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009311594
http://hdl.handle.net/11536/78065
顯示於類別:畢業論文


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