適合可攜式應用之超輕量數位訊號處理器核心

Abstract

由於大多數的可攜式多媒體裝置皆是以電池為其動力來源，因此一顆低功耗的精簡數位訊號處理器是不可或缺的。這篇論文提出一個極輕量的數位訊號處理器核心以及其根據不同的校能需求可擴展(scalable)的架構。此外，這篇論文同時提出一個具複雜度感知(complexity-aware)的程式碼自動產生器，並在其中使用一些演算及數值的最佳化技巧。在我們的模擬中，執行有限脈衝長度濾波器(FIR filtering)時我們所提出的數位訊號處理器核心只需要1.4個運算動作來處理每個tap的運算，即可達到跟有乘加器的(MAC-based)數位訊號處理器核心(每個tap需要一個運算動作)相當的濾波器品質。而且在TSMC 13μm CMOS的製程下，只需要80%~90%的運算時間，以及可節省13%~14%4的能量。最後，我們完成了一個有AMBA AHB相容介面數位訊號處理器核心。在TSMC 13μm CMOS製程下的實作是操作在400MHz，而功率消耗為22mW。包括256bytes記憶體的核心大小為0.6×0.6mm2。

The proliferation of portable and mobile multimedia devices powered by batteries demands compact and low-power digital signal processors. This thesis presents an ultra lightweight DSP engine, which performs multiplier-less DSP arithmetic. The architecture is highly scalable for various performance requirements. Moreover, an integrated complexity-aware code generator is proposed, where various algorithmic and numerical optimizations are implemented. In our simulations, the proposed DSP engine with the integrated code generator needs only 1.4 operations/tap for FIR filtering, which can achieve comparable quality of MAC-based ones (i.e. 1 operation/tap), and the performance can be converted into 80%~90% computing time savings and 13%~14% energy reductions from MAC-based DSP engines in the TSMC 0.13μm CMOS technology. Finally, the complete DSP core has been designed with an AMBA AHB-compliant interface. The cell-based implementation in the TSMC 0.13μm CMOS technology operates at 400MHz (600MHz maximum) and consumes 22mW average power for typical FIR filtering. The core size is 0.6×0.6mm2 including 256 bytes memory.