完整後設資料紀錄
DC 欄位語言
dc.contributor.author陳勇竹en_US
dc.contributor.authorYung-Chu,Chenen_US
dc.contributor.author林大衛en_US
dc.contributor.authorDavid W. Linen_US
dc.date.accessioned2014-12-12T02:52:05Z-
dc.date.available2014-12-12T02:52:05Z-
dc.date.issued2005en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT009311636en_US
dc.identifier.urihttp://hdl.handle.net/11536/78106-
dc.description.abstractIEEE802.16 無線通訊標準中,於系統的傳送端訂定了前向誤差改正編碼的機制,藉此減低通訊頻道中雜訊失真的影響。通道編碼是本論文的重點。 本篇論文的前半部份重點在於,實現IEEE 802.16e OFDM所訂定的前向誤差改正編碼系統於數位訊號處理器(DSP)上,並且針對DSP平台的特性以及前向誤差改正編碼的演算法進行程式的改進。在此篇論文中,我們將標準中制訂的四個必備的前向誤差改正編碼系統,實現在以德州儀器公司所發展的DSP為核心的平台上。由於我們關注的重點在於程式的執行效率,因此簡短地介紹過我們使用的前向誤差改正編碼的演算法以及DSP平台的架構與軟體最佳化技巧後,我們將逐步地闡述如何在DSP平台上最佳化我們的程式。最後,前向誤差改正編碼的編碼器部份,經過改進後,於DSP模擬器上,可以到每秒8013K位元的處理速度,而解碼器的部份可以達到每秒769K位元的處理速度。 本論文後半部份強調IEEE 802.16e OFDMA中低密度奇偶校驗碼複雜度的降低。我們介紹一些分析低密度奇偶校驗碼的工具後,逐步地闡述低密度奇偶校驗碼傳統的解碼演算法,並且介紹一些降低解碼複雜度的演算法。最後我們在加成性白色高斯通道下模擬了各種調變與各種解碼演算法,並把模擬之結果與一些數學分析的結果做比較。模擬的結果顯示這幾個降低複雜度的演算法和傳統的解碼表現相當接近,甚至更好。若從性能,延遲時間,運算複雜度,延遲時間,及需要的記憶體的角度來看,我們可以彈性的挑選適當的解碼演算法來使用,以取得之間的平衡。zh_TW
dc.description.abstractIn the IEEE 802.16e wireless communication standard, a Forward Error Correction (FEC) mechanism is presented at the transmitter side to reduce the noisy channel effect. The focus is on the channel coding. The focus of the fist part of this thesis is DSP implementation of the FEC schemes defined in IEEE 802.16e OFDM standard and modifying FEC algorithms to match the architecture of DSP platform. We have implemented four required FEC schemes defined in the standard on the Texas Instruments (TI) TMS320C6416 digital signal processor (DSP). After a brief review of the algorithms, we describe the DSP hardware architecture and its software optimization techniques. We then explain how we optimize the FEC programs on the DSP platform step by step since the speed performance is our major concern. At the end, the improved FEC encoder can achieve a data processing rate of 8013 kbits/sec and the improved FEC decoder can achieve a processing rate of 769 kbits/sec on the TI C64xx DSP simulator. The focus of second part is the complexity-reduction for low-density parity-check (LDPC) codes defined in IEEE 802.16e OFDMA. We describe some tools to analyze the LDPC codes. We then explain the conventional decoding algorithm, and some reduced-complexity decoding algorithms. Finally, we simulate the LDPC codes for all kinds of modulation and decoding algorithms in AWGN and compare the simulation results with analytical results. Simulation results show that these reduced-complexity decoding algorithms for LDPC codes achieve a performance very close to that of conventional algorithm, or even better. We can flexibility select the appropriate decoding scheme from performance, computational-complexity, latency, and memory-requirement perspectives.en_US
dc.language.isozh_TWen_US
dc.subjectIEEE802.16ezh_TW
dc.subject通道編碼zh_TW
dc.subject里德-索羅門碼zh_TW
dc.subject迴旋碼zh_TW
dc.subject低密度奇偶校驗碼zh_TW
dc.subject複雜度zh_TW
dc.subject最佳化zh_TW
dc.subjectDSPen_US
dc.subjectChannel Codingen_US
dc.subjectReed-Solomon codeen_US
dc.subjectConvolutional codeen_US
dc.subjectLDPC codeen_US
dc.subjectcomplexityen_US
dc.subjectOptimizationen_US
dc.titleIEEE 802.16e OFDM與OFDMA通道編碼技術與數位訊號處理器實現之研究zh_TW
dc.titleResearch in Channel Coding Techniques and DSP Implementation for IEEE 802.16e OFDM and OFDMAen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
顯示於類別:畢業論文


文件中的檔案:

  1. 163601.pdf

若為 zip 檔案,請下載檔案解壓縮後,用瀏覽器開啟資料夾中的 index.html 瀏覽全文。