應用於超寬頻系統之低功率主動性相位分離器與混波器之設計

Abstract

本篇論文主旨在於利用標準0.18um CMOS製程設計適用於超寬頻系統前端接受器之低功率主動性相位分離器與混波器積體電路，此外並利用新設計的混波器架構結合低雜訊放大器組成低功率、低電壓窄頻接收器前端電路。2顆低功率超寬頻主動性相位分離器、1顆低功率、低電壓混波器結合主動性相位分離器與1顆低功率、低電壓接收器前端電路皆已經由晶片製作而被驗證。 主動性相位分離器方面採用全新的架構，不同於以往利用差動放大器架構來達成主動性相位分離器的方法，而是利用NMOS在上PMOS在下的串接方式，避免電流源的寄生效應，以大幅增加頻寬，且同時利用Current Reuse的方法，大幅降低了功率損耗，根據量測結果可以得到在Gain Error小於2 dB且Phase Error小於3度的條件下，可用頻寬高達8 GHz，而整個電路的功率損耗僅為1.44 mW且Supply Voltage為1.2 V，相較於傳統的主動性相位分離器功率損耗約為12 mW，已大幅節省約88％。 當主動性相位分離器其後接上混波器或其它可調式差動輸入電路時，將造成主動性相位分離器的輸出負載改變，故根據實際需要改良原本第一顆主動性相位分離器，將NMOS的Loading由原本的電阻改為工作在三極體區的PMOS，利用改變其Gate偏壓 (Vtune) 將其Rds改變，使其成為0~10 GHz抗製程變異與對應輸出負載變化的主動性相位分離器，根據模擬結果，在Gain Error小於2 dB且Phase Error小於3度的條件下，可用頻寬高達10 GHz，而整個電路的功率損耗僅為1.44 mW且Supply Voltage為1.2 V，Output Loading在25 ~ 200 歐姆的範圍下均可利用改變Tunable Resister (Rds)來達成預期的效能，Vtune每變化0.1 V, Gain Difference變化1 dB而Phase Difference變化1.5度。 混波器方面為了降低Supply Voltage，而將原本的Gilbert Mixer gm stage與 switch stage串接方式改為將LO與RF DC分流，使每個MOS接有足夠的Vds跨壓，並且為了在Low Power下工作，將LO由大訊號改為小訊號的方式，使得Mixer一直工作於subthreshold region，因在工作期間並無MOS turn off利用兩倍的Conversion Gain且加上大RL的方式來達到足夠的Conversion Gain，利用此新設計的混波器分別完成了Low Voltage 1.5 mW 6~10.6-GHz UWB CMOS Mixer With Active Balun與 Low Voltage 0.86 mW 5~6 GHz Front End。 根據量測結果 Low Voltage 1.5 mW 6~10.6-GHz UWB CMOS Mixer With Active Balun在功率損耗為1.56 mW且VDD=1.2 V下提供平坦的Conversion Gain為10 dB ± 1.5 dB from 6 GHz to 10 GHz， NF 約為 15 dB 而 IIP3 約為 3 dBm。 Low Voltage 0.86 mW 5~6 GHz Front End量測結果則為，在 supply voltage 為 1 V 且功率損耗為0.86 mW下，最大的conversion gain 為 25 dB at 5.3 GHz， 3 dB 頻寬為 1 GHz， NF約為12 dB 而 IIP3 大約 -6 dBm。

The aim in this thesis is mainly based on the design of active balun and mixer in the receiver front end of ultra-wideband system using standard 0.18um CMOS process. Also, a low power low voltage narrow band front end is composed of a new mixer and a low noise amplifier. Two low power UWB active baluns, one low power mixer combined with a low power active balun and one low power low voltage front end were verified through 4 individual chips. In the first chip, an 8 GHz Low Power Ultra-Wideband Active Balun is analyzed and designed. We employ a new topology to design active balun and greatly reduce power consumption and extend the available bandwidth. Measured data show that the bandwidth extends to 8 GHz, gain difference is less than 2 dB, phase difference is less than 3 degree and differential gain has flat gain about -2 dB while consuming 1.5mW. In the second chip, an ultra wide band low power tunable active balun for process variation compensation is analyzed and designed. A tunable active resister is adopted to improve the first chip. Measured data show that the active balun has a tunable function for process variation compensation is its most important property. In the third chip, a new design of a low power low voltage mixer is combined with an active balun of the first chip. All transistors in the mixer are biased in the subthreshold region to approach low power application. Use large resisters about 800 Ω as output loading to have high conversion gain and the gain of balun and mixer compensate each other to form a flat gain from 6 to 10 GHz. Measured data show that the flat conversion gain is 9.5 dB ± 1.5 dB from 6 GHz to 10 GHz, NF is about 15 dB and IIP3 is about 3 dBm while consuming 1.5mW. In the final chip, a 5~6 GHz low power receiver front-end circuit is analyzed and designed. Employ the mixer of the third chip and modify the mixer from double balance to single balance. The single input mixer combines with a single output LNA and all supply voltages are reduced to 1 V to form the 5 ~ 6 GHz 1V low power receiver front-end circuit. Measured data show that the max conversion gain is 25 dB at 5 GHz, 3 dB bandwidth is about 1 GHz, NF is about 10 dB and IIP3 is about -6 dBm while consuming 0.8mW.