標題: 數位電視廣播之通道估測與等化器設計
Design of Channel Estimation and Equalizer for DVB-T/H
作者: 洪子捷
Tzu-Chieh Hung
周世傑
Shyh-Jye Jou
電子研究所
關鍵字: 數位電視;通道估測;等化器;多工正交;手持系統;DVB;channel estimation;equalizer;OFDM;handheld
公開日期: 2007
摘要: 在地面及手持式數位電視傳播系統中,通道估測以及等化器在接收端佔了很重要的角色,尤其在手持系統中,傳統的設計將無法應付通道的時變性,但是太過於複雜的設計又會對手持系統造成負擔。為因應時變通道之影響,並考慮硬體上對手持系統的負擔 ,本篇論文提出了一個新的通道估測演算法,以求在只增加些許硬體複雜度的前提下來降低時變通道的影響。此演算法藉由“預先決策”的方式降低計算虛擬領航碼時的誤差,更加上“停而做”的演算法,來減少決策錯誤時的代價,而此演算法能應用在各種傳統的通道估測法上,增加通道估測的準確度約7%至11% (BER)。而在硬體的實現上,本篇論文以無除法之原則,實現該演算法,並簡化了“停而做”的硬體架構,以達到低複雜度之目標。使用0.18微米之CMOS製程,此新演算法所增加的面積為150034平方微米約15154個邏輯閘,佔原本接收器的面積約7.3%。
In DVB-T/H system, channel estimation plays an important role in DVB receiver. Especially in hand held system, time variant channel will cause the distortion of the transmitted signals. Thus, a new channel estimation algorithm is proposed in this thesis to reduce the distortion of the transmission in the variant channel. This algorithm use the concept “Pre-Decision” to reduce the error of the virtual pilots. Moreover, the concept “Stop-And-Go” is used to reduce the penalty when the wrong decision is made. This channel estimation method can be combined with those traditional channel estimation methods. By adopting this algorithm, the performance can be improved about 7% to 11% (BER). For hand held system, low hardware complexity is the design target. In this thesis, division-free design is used in the hardware architecture and the architecture of Stop-And-Go is also simplified to reduce the complexity of hardware. Using 0.18 um CMOS process, the area of Pre-Decision block is 150034 um2 and the gate count is 15154. Thus, the area of Pre-Decision block is about 7.3% of the original receiver area.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009311652
http://hdl.handle.net/11536/78121
顯示於類別:畢業論文


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