高速及面積最小化之可組態加法器設計

Abstract

在數位電路系統設計中，加法是最基本的算術運算之一。因此過去有多種演算法及架構被提出來用以符合不同的設計需求。採用不同的加法器架構像是進位選擇(carry-select)式、平行前綴(parallel-prefix)式、和進位提前預知(carry-lookahead) 式會有不同的面積、速度、還有功耗表現。一般而言，如果想要得到較佳的速度及對後段製程實現較容易的電路結構，則Kogge-Stone平行前綴加法器架構是一套不錯的解決方案。在進位的產生方面，我們提出的架構利用了Ling加法器去縮減一個邏輯閘的延遲時間。而且我們用混合式平行前綴(hybrid parallel-prefix)/進位選擇(carry-select)架構及一些特殊的功能元件用以縮減整個加法器的面積。從實驗的結果可看出我們的新架構比傳統Kogge-Stone平行前綴加法器面積縮減了25%。近來,多媒體已在我們生活當中扮演了一個重要角色。在處理多媒體訊號方面需要一個可即時調整成處理不同精準度運算的高速可組態加法器。然而，為了達到可組態所使用的切割架構(partition scheme)是需要一些額外的負擔。因此，我們也提出了經由修改本來的架構但卻不需付出太多額外面積及延遲時間的新可組態式架構。從實驗數據可看出我們只需要多增加5.12%延遲時間及3.98%面積就可完成新的可組態加法器。簡而言之，我們所提出的加法器能在不影響速度下又盡可能的去縮減面積，且又容易拓展成可組態架構。

Binary addition is one of the fundamental arithmetic operations in digital system design. Consequently, several adder architectures have been proposed to meet different design requirements in the past. Various architectures like carry-select, parallel-prefix, and carry-lookahead lead to different performance among area, delay, and power. In general, Kogge-Stone parallel-prefix adders provide a good solution to optimize delay and regular structure for VLSI implementation. The proposed architecture uses Ling addition to reduce one logic level delay in parallel-prefix structure for the carry generation. Furthermore, using hybrid parallel-prefix/carry-select architecture and some special function blocks can reduce overall area. Experimental results reveal that the proposed architecture achieves 25% area reduction when compared to traditional Kogge-Stone parallel-prefix adders. Recently, the multimedia plays an important role in our life. Multimedia signal processing usually needs a fast reconfigure adder, which can be run-time reconfigured to handle the operations with different precisions. However, the extra overhead of partition scheme for the purpose of reconfigurability is unavoidable. Therefore, we present a new reconfigurable approach by modifying our original architecture without introducing significant extra area and timing penalty. Finally, experimental results show that the new reconfigurable adder needs only 5.12% delay penalty and 3.98% area penalty. In brief, the proposed adders do our utmost to reduce area without affecting speed and extent to reconfigurable scheme easily.