用於H.264視訊解碼器之記憶體控制器與熵解碼器之設計

Abstract

近年來，數位視訊科技逐漸普及並廣泛得使用在日常生活中。隨著對於更佳編碼效率的需求，H.264/AVC被視為下一代的國際視訊編碼標準。和之前的標準相比，如：MPEG-2和MPEG-4，新的標準藉由各式先進編碼工具明顯降低資料量並維持相同的視訊品質。對於這些技術，特別是框外預測，視訊解碼器系統需要在有限的短時間內存取大量的資料。由於數量的龐大，視訊資料存於晶片外之記憶體，而這些記憶體通常效能較差，因此系統效能高度依賴於外部記憶體與解碼器之間的頻寬。此外熵編碼技術的可變長度編碼特性造成了另一個系統效能的瓶頸，因為在硬體設計上這很難直接運用平行化和管線化來加速。

為了解決上述的問題，我們首先提出一個考慮到資料對應的記憶體控制器藉由要求內與要求外的最佳化，來改善外部記憶體的頻寬。結果，對於大小格式為525SD，QP為20的視訊序列，失誤率為1.8%，而完成即時明度與彩度動態補償所需的頻寬為46.96MBps。第二，我們設計了一個採用部份多重符號解碼，零跳躍以及跳躍式合併操作的熵編碼技術解碼器，它能夠減少需要的處理時脈，和其它已發表的CAVLC解碼器相比，最高可減少76%。在硬體的成本方面，CAVLC解碼器需要大約11K的邏輯閘，而UVLC解碼器需要1.8K。藉由提出的兩個關鍵模組，系統效能可以被有效的提升，特別是那些需要較低功耗與較高視訊品質的應用。

In recent years, digital video technology becomes popular and is widely used in our daily life. With demand of better coding performance, H.264/AVC is regarded as the international video coding standard for next generation. Comparing with prior video standards such as MPEG-2 and MPEG-4, the new standard achieve significant bit-rate reduction while still maintain the same video quality with various advanced coding tools. With these techniques especially for inter prediction, a large amount of data within a tightly bounded time is demanded in the video decoder system. Due to the large quantities, video data are stored in off-chip memories, that are usually slow, and thus the system performance strongly depends on the memory bandwidth between decoder and external memory. Besides, the variable length coding characteristics of entropy decoding builds another bottleneck in overall system since it is difficult to speedup the hardware design by directly applying parallelism and pipelining.

To solve above problems, we first proposed a data mapping aware memory controller to improve the external memory bandwidth with the optimized operation of both intra and inter request issues. As a result, the miss rate is about 1.8% for 525SD video sequence format with QP = 20 and the required bandwidth is 46.96MBps for real-time decoding of luma and chroma motion compensation. Second, a entropy decoder, which employee the techniques such as partial multi-symbol decoding, zero skipping and skipped merging operation of runs and levels, is designed to reduce the required processing cycles by up to 76% for the QP=28 case when compared with other CAVLC decoder designs. The hardware cost in gate count is about 11k for CAVLC decoder and 1.8k for UVLC decoder. With these two proposed key modules, the system performance can be greatly enhanced especially for the applications with demand of lower power consumption and higher video quality.