標題: | Hardware-assisted Syntax Decoding Model for Software AVC/H.264 Decoders |
作者: | Wu, Ming-Ju Chen, Yi-Tseng Tsai, Chun-Jen 資訊工程學系 Department of Computer Science |
公開日期: | 2009 |
摘要: | In this paper, we have proposed an efficient hardware-assisted syntax decoding model for software-based video decoder. The proposed syntax decoding model is a generic model for different video codec standards. The syntax decoding process is divided into codec-dependent high-level syntax parser and generic entropy decoding engines. Currently, the design is implemented specifically for the support of AVC/H.264 standard (for both CAVLC and CABAC acceleration). Nevertheless, the design of the proposed syntax decoding model has the potential of becoming the design of a flexible bitstream parser, which is the most challenging problem in the MPEG Reconfigurable Video Coding (RVC) Framework A Virtex-5 FPGA development board is used to implement and verify the full hardware-software system (including the hardware entropy engines and the software syntax parser and macroblock data reconstruction modules extracted from JM12.2). |
URI: | http://hdl.handle.net/11536/16369 |
ISBN: | 978-1-4244-3827-3 |
期刊: | ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5 |
起始頁: | 1233 |
結束頁: | 1236 |
顯示於類別: | 會議論文 |