區塊渦輪編解碼器設計與實現

Abstract

本論文為區塊渦輪碼(Block Turbo Code)編解碼器電路設計之研究, 原區塊渦輪編碼演算法裡, 每一個迴圈計算時皆需要實驗性參數來修正計算量, 針對此本論文提出了一個類幾何演算法取代實驗性參數修正計算量的方式, 所提出來的新演算法亦適合硬體電路實現。我們設計的範例是以WiMAX為本論文電路應用, 並考量及提出電路平行化處理方法在有限的硬體資源限制下達到我們要的效能。 本篇論文電路設計流程平台不單只以C語言來實現我們演算法階層的創意, 及用硬體描述語言Verilog來實現新的硬體架構, 我們也同時使用了SystemC的驗証平台來減少我們電路架構驗証所需時間, 且SystemC所建的模組亦提供未來電子系統層級電路設計使用。

In this thesis, a block turbo code of 802.16e is proposed. Unlike the conventional decoding algorithm requiring empirically derived parameters, the proposed geometric-like algorithm uses hamming distance to compensate the information. Not only improving the error performance, the proposed algorithm also facilitates hardware implementation. Moreover, a design methodology for parallel architecture is presented to meet various throughputs. The memory accessing hazard in parallel architecture can be overcome by the proposed multi-bank-array algorithm. The proposed algorithm is a partition and scheduling technique without extra memory. By the proposed algorithm and parallel design methodology, the block turbo code encoder and decoder defined in WiMAX(802.16e) is implemented. Note that, a design flow from algorithm level (in C language) to hardware level (in Verilog ) is presented. A systemC model is also built to provide a more efficient verification strategy and allows electronic system level design.