適用於高速行動之無線都會區域網路之基頻接收機設計

Abstract

近來，分集技術（diversity techniques）於無線通訊網路系統上受到各方矚目。使用多根妥善分隔的天線於傳送端與接收端時，多輸入多輸出（multi-input multi-output; MIMO）系統可以明顯地提升頻譜效率與系統傳輸能力。而空時分組碼（space-time block code; STBC）已被廣泛地應用於正交分頻多工（orthogonal frequency-division multiplexing; OFDM）系統上以得到傳送分集的增益效果，並改善無線通訊系統之系統效能。IEEE 802.16e標準已經採納空時分組碼與正交分頻多工系統結合之系統應用（STBC-OFDM systems）。該標準為IEEE 802.16-2004標準之延伸，主要是為了支援無線都會區域網路之移動性而提出的修正規格。在STBC-OFDM系統上，分集結合（diversity combing）、同調偵測與解碼（coherent detection and decoding）需要相當精確的通道狀態資訊（channel state information; CSI）。然而，精確的通道狀態資訊於行動無線通道上卻很難獲取。 在此論文中，我們提出應用於行動模式IEEE 802.16e規格之下行基頻接收機設計方法，並且此基頻接收機可應用於兩根傳送天線與一根接收天線（2×1天線）之STBC-OFDM系統上。主要目標是為了能提供高系統效能傳輸於車速達120 km/hr行動環境中。首先，我們提出簡單但有效之符元邊界偵測與載波頻率漂移估計方法。接著，提出精確且擁有可接受的硬體複雜度之兩階段通道估測策略，並且此種通道估測方法在與內插式通道估測方法比較上有明顯的傳輸效能提升。此論文所提出之基頻接收機經由2×1天線之STBC-OFDM系統模擬驗證。在車速120與240 km/hr的環境中應用於四相位偏移調變（quadrature phase shift keying; QPSK）之下，此接收機仍可分別達位元錯誤率（bit error rate; BER）約10-3與10-4，並且未使用任何通道編碼技術。我們以90 nm CMOS製程實現此接收機晶片。在16正交振幅調變（16 quadrature amplitude modulation; 16-QAM）下，此晶片最快可支援下行資料傳輸達27.32 Mbps。在通道估測硬體設計上，我們提出前置碼匹配（preamble match）、直接式多路徑干擾消除解相關器（straight multipath interference cancellation-based decorrelator）、最小平方估測器（least square estimator）及通道路徑解相關器（path decorrelator）等新的架構設計有效地減少硬體面積需求與功率消耗。此接收機晶片核心面積為2.4×2.4 mm2。在78.4MHz的操作頻率與1 V工作電壓下，其功率消耗為68.48 mW。 此外，我們提出一組用於串列傳輸之傳輸碼，4-脈衝振幅調變對稱式傳輸碼（4-PAM symmetric code），其主要用於差動4-脈衝振幅調變信號串列傳輸系統。而此傳輸碼保留8B/10B之傳輸優點，如直流平衡之位元串列資料與提供足夠的時序資料給予接收端進行時序回復等特性，並具有效降低時脈回復時所產生的資料轉換邊界抖動之功能。此串列傳輸編、解碼器以 0.18 um製程實現，並証明若在接收端做時序回復時能夠有效的改善參考之時序資訊轉換邊界抖動達±25％資料轉換時間。此4-脈衝振幅調變信號串列傳輸編、解碼器之設計可分別操作於819 MHz與704 MHz並且源頭資料傳輸率可到達13.1 Gbps與11.3Gbps。

Recently, diversity techniques are receiving particular attention in wireless communication systems. By using well-separated antennas at the transmitter and/or receiver, the multiple-input and multiple-output (MIMO) systems can significantly increase the bandwidth efficiency and system capacity. Space-time block code (STBC) has suggested to be applied in an orthogonal frequency division multiplex (OFDM) system to utilize the transmit diversity for improving system performance in wireless communication systems. STBC-OFDM systems have been adopted in IEEE 802.16e which is an extension of IEEE 802.16-2004 for supporting mobility of wireless metropolitan area network (WMAN). However, for diversity combining, coherent detection and decoding, STBC-OFDM systems require accurate channel state information (CSI), which is particularly difficult to obtain in mobile wireless channels. This dissertation proposes a downlink baseband receiver scheme for IEEE 802.16e in mobile mode. The proposed receiver is applied in STBC-OFDM system with two transmit antennas and one receive antenna and aims to provide high performance under the vehicle speed up to 120 km/hr. First, the simple and robust symbol boundary detection and carrier frequency offset estimation schemes are proposed. Then, an accurate but hardware affordable two-stage channel estimation strategy is adopted to overcome the challenge of outdoor mobile channels. It has significant performance improvement as compared with the interpolation-based channel estimations. The performances of the proposed receiver have been demonstrated through the simulation of an STBC-OFDM system with two transmit antennas and one receive antenna. At vehicle speed of 120 and 240 hr/km for quadrature phase shift keying (QPSK) modulation, the proposed design can achieve the bit error rate (BER) of about 10-4 and 10-3 without using channel coding. The proposed receiver implemented in 90nm CMOS technology can support up to 27.32 Mbps (uncoded) downlink data transmission in 16 quadrature amplitude modulation (16-QAM). In the proposed channel estimator, novel architectures of a preamble match, a straight multipath interference cancellation (SMPIC)-based decorrelator, a least square (LS) estimator, and a path decorrelator are designed to reduce the area and power of the blocks. The receiver has the core area of 2.4×2.4 mm2 and dissipates 68.48 mW at 78.4MHz operating frequency from a supply voltage 1 V. In addition, a novel DC-balanced low-jitter transmission code, a 4-PAM symmetric code, for a 4-PAM signaling system is presented. The 4-PAM symmetric code preserves all the useful characteristics of 8B/10B transmission code, such as DC-balanced serial data and guaranteed transitions in the symbol stream for data/clock recovery. Moreover, the proposed method decreases the jitter of the timing transition of the data in the receiver. The design results using 0.18 μm process demonstrate that the new transmission code can decrease the jitter of the transition point by ± 25% of the transition region. The operation speeds of the encoder and decoder for the 4-PAM symmetric code are 819 MHz with 16-bit inputs (throughput 13.1 Gbps) and 704 MHz with 16-bit outputs (throughput 11.3 Gbps), respectively.