GPS接收器之頻率合成器設計

Abstract

本論文在實現GPS接收器的頻率合成器,其目的是要產生1.575GHz的穩定振盪訊號。本頻率合成器利用一石英振盪器振盪在24.61MHz之參考信號,經過相位檢側器、迴路濾波器、壓控振盪器及除法器(N=64)所組成的鎖相迴路系統,使得當迴路收斂時,壓控振盪器的振盪頻率為參考信號頻率的64倍,以產生GPS接收器所需要的高頻信號。 在頻率合成器之各功能方塊電路我們都使用差動型式的電路來實現, 以減少雜訊對高頻輸出信號的影響。我們以台灣積體電路TSMC 0.35 um BiCMOS Mixed Signal SiGe 3P3M製程來實現此頻率合成器,並針對製程環境模擬頻率合成器動態特性及相位雜訊(Phase Noise)與訊號劇動(Jitter)等之性能。在工作電壓為3.3v,整個頻率合成器消耗功率為38.5mW。本壓控振盪器振盪的頻率輸出範圍可從1.1GHz至2.8GHz,以防止當製程環境變動影響時,壓控振盪器無法合成預期高頻信號輸出;經觀察模擬結果,頻率合成器在各種不同邊緣模型(Corner Model)環境變動下仍可穩定輸出,當偏移頻率1MHz時所量測之相位雜訊為-106.2dBc/Hz。

In this thesis we design a frequency synthesizer which can generate a steady oscillating signal of 1.575GHz for GPS receivers. This frequency synthesizer uses a quartz for oscillation at 24.61MHz as the reference signal; this signal then is used as the input of a phase-locked loop composed of a phase detector, a loop filter, a voltage-controlled oscillator, and a divider with division ratio of 64 (N=64). When the loop converges, the VCO output signal frequency will equal 64 times of 24.61MHz. All functional blocks of this frequency synthesizer are realized by circuits of the differential type in order to lower the noise effect on the high-frequency output signal. The TSMC 0.35 um BiCMOS Mixed Signal SiGe 3P3M process is used to implement the frequency synthesizer; its model parameters are used to simulate the dynamic behaviors and obtain the performance parameters such as the phase noise and the phase jitter. The consumption power of the frequency synthesizer is 38.5mW with the 3.3V power supply. A wide range of VCO operation frequency, 1.1GHz-2.8GHz, is designed to ensure that the VCO still can generate the desired frequency even when the process conditions vary. Simulation results demonstrate that the synthesizer obtains a steady output signal under different corner models. The phase noise is obtained to be -106dBc/Hz.