标题: | 适用于Serial-ATA之展频时脉产生器及其内建自我测试电路 A Spread Spectrum Clock Generator and Built-in-Self-Test Circuit for Serial-ATA |
作者: | 周茂轩 MaoHsuan Chou 苏朝琴 ChauChin Su 电控工程研究所 |
关键字: | 除小数频率合成器;展频时脉产生器;内建自我测试电路;锁相回路;三角积分调变器;fractional-N frequency synthesizer;spread spectrum clock generator;built-in-self-test;phase-locked loop;sigma-delta modulator |
公开日期: | 2006 |
摘要: | 随着对高速传输速率需求的不断提升,高速时脉信号所造成的电磁干扰(Electro-Magnetic Interference, EMI)成为不可忽视的问题。在常见的外部储存规格Serial AT Attachment (Serial-ATA)中,系统要求资料传输时的时脉频率具有5000 ppm的展频量与30~33 kHz之三角波调变率。展频技术即是利用对时脉信号频率做调变以有效降低电磁干扰。 在本论文中,我们提出一个符合Serial-ATA规格并适用于6Gbps资料发送器之展频时脉产生器(Spread Spectrum Clock Generator, SSCG)及其内建自我测试(Built-in-Self-Test, BIST)电路。我们使用一个具备三阶三角积分调变器的除小数频率合成器来实现展频时脉产生器,使用数位式三角积分调变技术可将量化杂讯调变到高频以减少spur现象。为了减少展频时脉产生器的相位跳动,我们采用相位调变的方式来达到展频的效果。展频时脉产生器的内建自我测试电路是用数位的方式侦测展频时脉产生器的频率变动,藉由此测试电路可以简单的测试出展频时脉产生器是否正常操作。 我们使用TSMC CMOS 0.18 μm制程实现了一个1.2 GHz 10个phases,具有5000 ppm、30 kHz三角波调变的展频时脉产生器及其内建自我测试电路。在非展频情况所量测到的时脉抖动peak-to-peak jitter为48 ps;RMS jitter 为7.226 ps。在展频模式下,频谱上的时脉峰高能量降低了21.633 dB。 As operating at high frequencies, currents and voltages present in the circuits and the signal traces lead to a great Electro-Magnetic Interference (EMI). In Serial AT Attachment (Serial-ATA), one of the popular external storage specifications, it requires a wide spreading of 5000 ppm at a 30~33 kHz triangular modulation rate. The Spread Spectrum Clock Generator (SSCG) is a special technique of frequency modulation to reduce EMI effectively. In this thesis, we propose a SSCG for 6Gbps transceiver and its Built-in-Self-Test (BIST) circuit for Serial-ATA specification. We use a fractional-N frequency synthesizer with a digital third-order MASH 1-1-1 sigma-delta modulator to accomplish the spread spectrum function. The use of digital sigma-delta modulation technique in the fractional-N frequency synthesizer can eliminate spurs. Using phase modulation to spread the spectrum can reduce the phase jump of the SSCG. The BIST circuit for SSCG is a digital approach to detect the frequency variation of the SSCG, it can tests if the SSCG work or not effectively and precisely. The SSCG which has 1.2 GHz 10 phases, a 5000 ppm down spread and a 30 kHz triangular modulation rate. The BIST circuit are implemented using TSMC CMOS 0.18 μm technology. The measurement results show that the non spreading clock has a peak-to-peak jitter of 48 ps, a RMS jitter of 7.226 ps, and a peak amplitude reduction of 21.633 dB in the spread spectrum mode. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT009312579 http://hdl.handle.net/11536/78266 |
显示于类别: | Thesis |
文件中的档案:
If it is a zip file, please download the file and unzip it, then open index.html in a browser to view the full text content.