標題: 單級全橋式交/直流變通型轉換器之小訊號分析與並聯架構之電流均享設計
Small Signal Analysis of a Modified Single-Stage Full-Bridge AC/DC Converter and the Current Sharing Design in Paralleled Structure
作者: 陳彥廷
Yen-Ting Chen
張隆國
Lon-Kou Chang
電控工程研究所
關鍵字: 單級電源轉換器;全橋式電源轉換器;小訊號分析;single-stage converter;full-bridge converter;small signal analysis
公開日期: 2006
摘要: 本文旨在對一變通的單級全橋式交/直流電源轉換器作小訊號分析,並且以此電路為基本模組,於並聯架構中設計電流均享電路以實現模組擴充。該轉換器主要包含輸入電流修飾部分與全橋穩壓兩部分。電路主要特色為:使用一開關利用責任週期比加上盲點時間,來控制儲能電容電壓的最大值,並且修飾輸入電流提高電源側的功率因數。 文中針對此電路架構作開迴路小訊號分析,基於此小訊號分析,對轉換器設計迴授補償電路。並以此電路架構為基本模組,在輸入並聯輸出並聯的架構中,設計具有電流均享功能的電路。同時以Pspice模擬軟體,針對一部220V ac(r.m.s)輸入,且為660W/100V輸出的單級全橋式交/直流轉換器,並且符合規範IEC61000-3-2的雛形電路,進行電腦模擬以輔助相關的設計。
In this thesis, a detailed small-signal analysis of an improved single-stage full-bridge AC/DC converter, 220V input and 660W/100V output, is presented. A current sharing paralleled structure integrated by the proposed converters is also presented to realize an integrated power system. The converter was composed of two subcircuits: an input current shaper and a full-bridge regulator. The proposed circuit has two major merits: the maximum voltage across the bulk capacitor can be suppressed, and the input current satisfies IEC61000-3-2 Class A standard. The converters are connected in the input-parallel-and-output-parallel configuration. The system simulation and analysis had been successfully carried out in both Matlab and Pspice system for verification.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009312580
http://hdl.handle.net/11536/78267
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