使用全數位控制多相交錯式PWM技術之D類功率放大器實現

Abstract

本文研製一個以可規劃邏輯閘陣列(FPGA)為基礎之全數位控制交錯半橋式D類放大器，以解決在當開關切換頻率不夠快速下之電壓總諧波失真不佳的問題。所設計的控制器為包含數位補償器、同步取樣控制器及脈寬調變產生器三個子系統的系統。模擬平台採用Simulink軟體結合Modelsim軟體，除了驗證子系統的性能之外，也進行單相及交錯半橋式D類放大器模擬。實驗板使用Altera公司的實驗發展平台Cyclone II Development Kits，搭配軟核處理器NIOS II，可將實驗波形透過RS232傳送回Simulink，以及SPI等串聯介面，進行互動式的實驗。可藉由SPI介面設定控制器的參數，簡化了所設計數位控制器的腳位。本研究所提出之方法，主要在於以最佳控制方式降低高功率(>100W)之D類放大器在低開關頻率 (100kHz)的波形失真，模擬結果顯示所提出控制方法之有效性，當脈寬調變波形解析度為10位元且開關切換頻率為100kHz時，且無效時間設定0.5μs，輸入訊號由1kHz至20kHz，滿載輸出電壓總諧波失真均低於1.3%，證明交錯式的架構確可在不提高切換頻率的條件下，可有效降低輸出電壓的總諧波失真。

This paper presents the research of an FPGA-based fully digital-controlled multiphase-interleaved class-D amplifiers. This topology could reduce the output voltage total harmonic distortion while the switching frequency is low. The proposed digital controller is composed of three subsystems which are digital compensator, digital PWM generator, and the synchronous sampling controller. The simulation platform which is combined with simulink and modelsim could fast verify the functionality of realized subsystems. It could also simulate the results of the single-phase or three-phase class d amplifiers which is connected with the proposed digital controller. The proposed control scheme has been implemented using an FPGA board (Altera Cyclone II Development Kits). It possesses the soft core NIOS II and variety usable IPs. We used the communication interface RS-232 and SPI to transmit parameters to the digital controller or receive sampled 本論文乃由國科會補助之計畫研究成果，計畫編號為94-2213-E-009-146。 data from the experimental board. These sampled experimental data could be plotted in the simulink. Simulation verification has been carried out on a single-phase and interleaved class-D amplifier. Under the 10-bit PWM resolution, 100kHz switching frequency and 0.5μs dead-time constraints. The Simulation results show a voltage THD of 1.3% at rated output. The simulation results show the feasibility and superiority of the proposed digital interleaved class-D control scheme.