三角積分類比數位轉換器之自我測試技術

Abstract

測試高解析度的類比數位轉換器(例如三角積分類比數位轉換器)成本是非常昂貴的，因為它需要使用非常先進的混合訊號測試機台、較長的測試時間、需超低雜訊的測試環境，且測試的設定也非常麻煩。此外，當此高解析度的類比數位轉換器被嵌入系統單晶片中，類比數位轉換器的可測性將非常糟。為了解決這些問題，內建自我測試技術的方法受到越來越多的關注。在此論文中，我們提出內建自我測試技術來解決三角積分類比數位轉換器的測試問題。

本論文第一部分，我們設計一內建自我測試技術的三角積分類比數位轉換器，這個轉換器使用了兩個技術，一是DfDT的技術，此技術可讓轉換器使用數位激發源來量測；另一是我們提出的改良式CSWF技術，它可以讓我們在時域上分別計算轉換器的信號功率和總諧波失真加雜訊功率。和傳統的快速傅立葉轉換分析法相比，我們提出的技術並不需要強大複雜的CPU、DSP或內嵌大容量的記憶體，新增加的內建自我測試電路完全是數位的，且僅佔11.9 K的Gate數。而為了證明這個含自我測試技術的三角積分類比數位轉換器的測試能力，我們建立一個待測物原型，包含了使用DfDT技術的三角積分類比數位轉換器晶片和一塊用來嵌入其他數位電路的FPGA板。

結果顯示，我們所提出的內建自我測試技術和傳統快速傅立葉轉換方法比較，所量測的信號與雜訊加失真比值只有0.3 dB的差距。在測試的動態範圍值，兩種方法是相同的。此外，所提的內建自我測試技術擁有額外增加的面積小、高測試準確性和靈活調整激發源之內建自我測試應用的重要功能。

雖然提出的內建自我測試技術設計是非常成功的，但我們注意到使用數位方法量測到的信號與雜訊加失真比值和用類比方法量測到的值仍然有差距，尤其當輸入的激發源振幅越大時，差距越大。

因此本論文第二部分，我們探討DfDT架構，發現數位激發源的shaped noise是信號與雜訊加失真比值降低的原因。為了降低數位激發源shaped noise的影響，我們提出了改善數位測試準確性的一個新D3T架構，用以取代DfDT。使用D3T架構的轉換器擁有兩個模式；一是正常模式，一是數位測試模式。在數位測試模式下，擁有D3T架構轉換器的輸入開關電容網路，被重新設定為兩個數位電荷轉換器，每個數位電荷轉換器可接收被三角積分轉換器調變過後的數位串列當作它的激發源。藉著輸入兩個擁有相同的數位串列但不同相位延遲的訊號，使得用D3T架構的轉換器相當於是用一個經過低通濾波器的類比激發源量測。因此，擁有D3T架構的轉換器降低了數位激發源的shaped noise，並提高了測試精準度。

我們製造了測試晶片來證明使用D3T架構的有效性。使用數位方法測量的結果顯示，在超取樣128的狀態下，最大的信號與雜訊加失真比值為80.1 dB，且除了在-3 dBFS情況下，使用數位和類比方法測量的結果差距均在1.9 dB以內。此外，使用D3T架構的轉換器僅增加18個類比開關，且因它在這兩種模式的負載和使用的元件幾乎相同，因此擁有高故障觀測性和全速可測性。

Testing high resolution analog-to-digital converters (ADCs) such as Σ-Δ modulators is very costly because of the requirements of a high-end mixed-signal automatic test equipment (ATE) and a long test time. Besides, the test setup is also very bothersome since the cost of an ultra-low noise testing environment is substantial. Furthermore, the testability of the ADC under test (AUT) becomes worse when the high resolution AUT is embedded in a complex system-on-chip (SoC) device. To address these issues, build-in self-test (BIST) techniques are drawing more and more attention. In this dissertation, we propose the BIST techniques for Σ-Δ ADC to address these testing issues.

The first part of this dissertation proposes a BIST Σ-Δ ADC design. The AUT is a second-order design-for-digital-testability (DfDT) Σ-Δ modulator. The DfDT scheme enables the AUT to be tested by the digital stimuli. The BIST circuity uses the proposed modified controlled sine wave fitting (CSWF) procedure to calculate the signal power and the total-harmonic-distortion-and-noise power in time domain separately. Compared with the conventional Fast Fourier Transform (FFT) analysis, neither complex CPU/DSP nor bulky memory is required. The added BIST circuitry is purely digital and the hardware overhead is as low as 11.9 K gates. A prototype comprising the second-order DfDT Σ-Δ modulator chip and an FPGA board which implements the digital functions is used to demonstrate the effectiveness of the BIST design.

Measurement results show that the signal-to-noise-and-distortion ratio (SNDR) difference between the conventional FFT analysis and the proposed BIST design is only 0.3 dB. Furthermore, the tested dynamic range values by both methods are the same. The proposed BIST implementation achieves the advantages of compact hardware, high test accuracy, and the flexibility of adjusting the stimuli which are important features for BIST applications.

Although the BIST design is very successful, we notice that the digital tests present somewhat lower SNDR than that of the conventional analog test. The most significant difference between the digital tests and the corresponding analog tests is found in the the tests with the largest stimuli.

In the second part of this dissertation, we investigated the root causes of the SNDR difference and found the shaped noise of the digital stimulus reduces the BIST accuracy. To alleviate the impacts of the shaped noise of the digital stimulus, we proposed a decorrelating design-for-digital-testability (D3T) scheme to replace the DfDT scheme for Σ-Δ modulators so as to improve digital test accuracy. The modulator under test (MUT) employs the D3T scheme has two operation modes: the normal mode and the digital test mode. In the digital test mode, the input switched-capacitor network of the D3T modulator is reconfigured as two sub-digital-to-charge converters (sub-DCCs). Each of the sub-DCCs accepts a Σ-Δ modulated bit-stream as its test stimulus. By inputting the two sub-DCCs with the same Σ-Δ modulated bit-stream but with different delays, the MUT is equivalently tested by the result of filtering the bit-stream with a finite-impulse-response low-pass filter. Consequently, the D3T MUT suffers less from the undesired shaped noise of the digital stimuli, and enhances the test accuracy.

A test chip has been designed and fabricated in order to verify the effectiveness of the proposed D3T scheme. The measurement results show that the MUT achieves a peak SNDR of 80.1 dB using the digital tests at an oversampling ratio of 128. The differences of the SNDR values in the digital and conventional analog tests are no more than 1.9 dB except for the -3 dBFS test. The analog hardware overhead of the D3T MUT consists of only 18 switches. In addition, the D3T scheme also provides a high fault observability and at-speed testability, because most of the MUT's components are active and have the same loads in both modes.