應用於超寬頻接收機之低電壓低功率低雜訊放大器與多頻帶頻率合成器

Abstract

本論文的第一部份分三個方面研究超寬頻低雜訊放大器電路設計方法，包含輸入匹配，雜訊指數和功率增益，並且以電路元件來表示這些特性。實作的超寬頻低雜訊放大器顯示3.1 ~ 10.6GHz具有小於-7.07dB輸入返回損耗以及-12.5dB輸出返回損耗，在2.5 ~ 8.5GHz具有10dB增益，3dB頻寬約為2 ~ 9 GHz，最小雜訊指數為3.46dB，並且在1V的供給電壓下，放大器功率消耗為7.25mW。 在第二部份，針對低相位雜訊設計一初始應用於超寬頻系統之頻率合成器，可分別產生頻率8448MHz、4224MHz和2112MHz。利用0.18微米CMOS製程實現，於三頻帶量測之相位雜訊小於-121dBc/Hz@1-MHz，可調頻寬約為10%。於1.8V的供給電壓下，總功率消耗為52.2mW。 此外，設計一應用於多頻帶正交分頻多工超寬頻系統之頻率合成器，從3 ~ 10GHz具有12個可選擇頻帶，於此架構中，完成四相位壓控震盪器之模擬相位雜訊小於-107dBc/Hz@1-MHz，可調頻寬為7.93 ~ 10.3GHz。主要頻率輸出功率與旁路頻帶模擬相差至少35dB。在1.8V的供給電壓下，核心電路消耗81.1mW，緩衝器消耗32.6mW。模擬頻帶切換時間約為1ns。

In the first part of the thesis the design method of UWB LNA topology is studied and analyzed in three respects, including input matching, noise figure and power gain. These characteristics are expressed in terms of circuit elements. The implemented UWB LNA demonstrates S11 < -7.07dB and S22 < -12.5dB from 3.1 to 10.6 GHz. The power gain (S21) is 10dB from 2.5 to 8.5 GHz, the 3dB bandwidth is 2-9 GHz. The minimum noise figure is 3.46dB while consuming 7.25 mW with bias voltage of only 1V. In the second part, an initial direct frequency synthesizer structure for UWB is designed with low phase noise performance, and three LO bands (8448MHz, 4224MHz and 2112MHz) are produced individually. Fabricated in 0.18-μm CMOS technology, in three LO bands, this work achieves the measured phase noise of less than -121dBc/Hz@1-MHz offset and the frequency tuning range of 10% while consuming 52.2mW from a 1.8-V supply. Furthermore, a direct frequency synthesizer with 12 selective bands from 3 to 10 GHz is designed. In this prototype, we achieve QVCO’s simulated phase noise less than -107dBc/Hz@1-MHz offset and the tuning range from 7.92 ~ 10.3 GHz. The simulated output powers of twelve bands have better than 35 dB sideband rejection while consuming 81.1mW of the core circuit and 32.6mW of the buffer from a 1.8-V supply. The simulated switching time for hopping frequency is about 1ns.