2.45-GHz低電壓(0.7V)低功率摺疊切換式混頻器

Abstract

由於無線通訊市場的蓬勃發展，以及CMOS製程技術的快速提升，使得傳統上利用GaAs或SiGe製程來設計的射頻積體電路也能夠在CMOS的製程下實現。此一進步使得無線接收機的射頻前端電路能夠跟基頻電路整合成單一晶片，大大地減少了電路面積以及成本。但是由於隨著製程進步持續降低的供應電壓使得射頻積體電路很難滿足接收機的訊號動態範圍，因此需要研究新的架構使得射頻前端電路能夠操作在低於1V的供應電壓環境下，如此才能更進一步的跟基頻電路整合。 因此我們使用一個新型的摺疊切換式混頻器，藉由它能操作在低於1V的供應電壓下，將此混頻器應用在低電壓低中頻接收機架構中。此混頻器可以提供8.99dB的轉換電壓增益，以及良好的線性度(P1dB= -9dBm，IIP3=4dBm)，消耗功率為2.87mW，晶片面積為1.24 × 1.19 mm2。本論文中的晶片使用標準的0.18-μm CMOS製程設計和實作，並且在國家晶片系統設計中心完成量測。

Wireless and mobile communications is one of the fast growing microelectronics applications. Traditionally, the RFICs are implemented in GaAs or SiGe process. With the progress of scaled down CMOS technology, RFICs can be implemented in CMOS process and provide high integration and low cost. Under reduced supply voltages, many circuit topologies of the RF front-end can not meet the stringent dynamic range of wireless receiver. It needs more efforts toward finding out new topology suitable to operate at sub-1V supply voltage. In this thesis, we analyze the design of low-voltage folded-switching mixer and employee it to the proposed low-IF receiver RF front-end. The new mixer has high voltage gain (8.99dB), moderate noise figure (10.3dB in simulation), moderate linearity (P1dB = -9dBm, IIP3 = 4dBm), and low power consumption (2.87mW). The total chip size is 1.24 × 1.19 mm2. This chip is designed and implemented in CMOS 0.18-μm 1P6M technology and measured in National Chip Implementation Center (CIC).