低功率 3.1 ~ 15 GHz 超寬頻混波器

Abstract

本論文主要是在研究低功率超寬頻混波器的設計，頻段則是設計在3.1~15GHz，設計方法包含以下幾種步驟，(一)輸入匹配 (二)混頻器主架構的選取 (三) current injection配合低功率的設計 (四)偏壓的選取 (五)訊號走線的寄生效應 (六)Switch stage對雜訊與增益的影響。在設計的過程中遇到了許多的問題，特別是在架構的選取會影響直流偏移的問題，進而影響輸出訊號及準位等等，論文中會解釋如何克服這些問題。電路設計在頻帶3.1GHz ~ 15GHz，而基頻頻率則是設計在10MHz時，在量測的結果為電壓轉換增益約-0.7 ~ 6.1左右、射頻輸入返回損耗為-10dB以下、切換級輸入返回損耗為-14dB以下、P1dB分布在-15 ~ -13dBm內在頻帶4GHz ~ 10GHz、以及1 ~ 3 dBm的 IIP3在頻帶4GHz ~ 10GHz，且此電路設計電路功率僅消耗17.5mW，本電路使用台積電 0.18um CMOS製程設計，並且在國家晶片系統設計中心量測，其模擬設計與量測結果的差異在論文中做一些說明和討論。

The topic of this thesis is to research the design of the low-power ultra-wideband mixer. The bandwidth is designed from 3.1GHz to 15 GHz. The design procedures include: (1) input matching networks (2) choice of architecture (3) current injection matches for the design of low power (4) choice of the bias point (5) parasitic effect of the signal’s routes (6) influence of noise figure and conversion gain with switch stage. When designing the ultra-wideband mixer, many problems are found. Especially, the DC Offset will be influenced by the architecture. And then the DC and signal of the output will be influenced, etc. The design procedures will explain how to conquer these problems in detail. This circuit is designed from 3.1 to 15 GHz. And IF is at 10MHz. The measurement results include: Conversion voltage gain is about -0.7 ~ 6.1 dB. RF input return loss is better than 10dB. The return loss of switching stage is better than 14dB. P1dB is about -15 ~ -13dBm from 4GHz to 10GHz. IIP3 is about 1 ~ 3dBm from 4GHz to 10GHz. Power consumption of the circuit is only 17.5mW. This circuit is fabricated in TSMC 0.18um CMOS. The circuit is measured at CIC. There are some discussion and statement about difference between simulation and measurement in this thesis.