應用於數位電視寬頻調諧器之三角積分調變頻率合成器

Abstract

近年來，射頻積體電路(RFIC)技術迅速地發展演進。由於低成本以及低功率消耗等優點，射頻積體電路在於無線通訊上的應用更是引人注目。在設計發射機系統時的ㄧ大挑戰，便是在於如何合成所需要的任何本地震盪源(LO)訊號。因此，頻率合成器隨即被發展出來以解決此種需求。 論文中提出分析ㄧ個整合於單一晶片，無須外掛其他被動元件的三角積分調變除小數頻率合成器。此頻率合成器是以TSMC 0.18-微米互補式金氧半製程製造，可以合成1.27 GHz到2.08 GHz頻帶範圍，提供數位電視系統135個頻道切換。模擬結果以及量測數據將會在內文中加以討論、解釋。 本論文主要區分為五部分。第一部分介紹數位電視系統相關知識。第二部分探討鎖相迴路以及三角積分調變基本原理。我們將著重於電路設計概念以及介紹一些現有的技術。第三部分呈現頻率合成器架構和組成方塊，包含修正後的壓控振盪器、相位檢測器、電荷幫浦、迴路濾波器、可程式除頻器以及三角積分調變器均會詳細地介紹。第四部分展示模擬及量測結果。最後，針對此次結果我們作ㄧ總結。對於未來可行的改良建議事項將列於論文的最後作為結束。

Radio Frequency Integrated Circuits (RFIC) have been progressed rapidly in recent years. RFIC becomes attractive for applications in wireless communication due to its low cost and low power. One of the major challenges in the design of the transceiver system is the frequency synthesis of the local oscillator (LO) signal. Therefore, the frequency synthesizer is developed for this purpose. In this thesis, a Delta-Sigma fractional-N frequency synthesizer in a single chip without any external discrete components is proposed and analyzed. The synthesizer was fabricated in TSMC 0.18μm CMOS process and can support all 135 channels of the DTV system from 1.27 GHz to 2.08 GHz. The simulation results and measurement data are discussed and explained in the content. The thesis is mainly divided into five parts. The first section introduces the related knowledge of the DTV system. The second section discusses the basic principle of the Phase-Locked-Loop and Delta-Sigma modulation. We focus on the important circuit design concepts and existent techniques. The third section presents the architecture and components of a frequency synthesizer. In this section, a modified voltage-controlled oscillator, a phase-frequency detector, a charge pump, a loop filter, a programmable divider, and a delta-sigma modulator are all described in details. The fourth section shows our simulations and measurement results. Finally, a conclusion to this work is given. Suggestions for future works are recommended at the ending of this thesis.