使用CMOS 0.18μm 技術設計一應用於多頻帶正交頻率多工超寬頻系統band group 5及一適用於IEEE 802.11a規格之整數型頻率合成器

Abstract

此篇論文主要探討了兩個電路設計，以及一個高整合性的多頻帶三角積分調變分數型頻率合成器。首先，設計一個使用1.5V供應電源應用於10GHz，多頻帶正交頻率多工超寬頻系統band group 5處的整數型頻率合成器，提供了9.29~10.9GHz的頻率調變範圍及-5.9dBm的輸出功率。壓控振盪器主要是由一組交互耦合的NMOS對與為了提高Q值而使用的中央抽頭式電感所構成。整個電路的相位雜訊為-97dBc/Hz@1MHz，頻率鎖定時間約為25μs，功率消耗為23.55mW。此外，電路中我們還額外設計一組暫存器，將控制訊號由七個轉換為兩個，有效地縮減電路所佔的面積。接著在第二部分我們探討802.11a整數型頻率合成器的設計。電路中的壓控振盪器使用堆疊的交互耦合NMOS與PMOS對，振盪頻率設計在4.95至5.82GHz之間，並藉由脈衝吞嚥技術器（pulse-swallow counter）來控制除數。只要調整外接的五個控制訊號即可有效地改變電路的總除數以達到所預定的振盪頻率。除此之外，設計一個外接的三階迴路慮波器除了考量在製程飄動的情況下尚能進行調整，低雜訊的要求也一併地考慮。鎖定時間大約是20μs，相位雜訊為-126dBc/Hz@1MHz，總功率消耗則是26.35mW。最後在附錄中我們介紹了一個利用50% 除頻方法將802.11a/b/g無線網路系統與GSM/DCS1800手機系統四個系統整合於單晶片中的頻率合成器。電路鎖定時間為30μs，相位雜訊為-114dBc/Hz@1MHz，總功率消耗105mW。

In this thesis, we will discuss two main circuit designs and present a highly integrated multi-band sigma-delta fractional-N frequency synthesizer. First, an integer-N frequency synthesizer operated at 10GHz around the MB-OFDM UWB system 5th band group with only 1.5V supply voltage which owns a varying frequency ranging from 9.29GHz to 10.9GHz and delivers -5.9dBm output power is shown. A single NMOS cross-coupled-pairs forms the core circuit of the voltage-controlled oscillator with a center-tapped inductor adopted to enhance the Q value at the same time, thus make the phase noise -97dBc/Hz at 1MHz. The frequency settling time is about 25μs and the whole circuit power consumption is 23.55mW. Besides, a register is designed to efficiently reduce the chip area by transferring the control signals from seven to two. In the second, we discuss about an 802.11a integer-N frequency synthesizer design. The oscillation frequency ranges between 4.95 and 5.82GHz while NMOS and PMOS cross-coupled pairs cascoded architecture is chosen in this design. The pulse-swallow counter is used to program the division number. As long as switching the five external control bits can we effectively adjust the total division and obtain the oscillating frequency expected. Additionally, a third order loop filter is design to be implemented off the chip preparing for the adjustment against fabrication variations and low noise consideration. The settling time of the circuit is about 20μs or so and the phase noise is -126dBc/Hz at 1MHz. The total power consumption is about 26.35mW. At last in the appendix shows an 802.11a/b/g WLANs and GSM/DCS1800 mobile system frequency synthesizer integrated in a single chip by 50% frequency division techniques. The settling time is 30μs and the phase noise is -114dBc/Hz at 1MHz. Total power consumption is 105mW. The measuring preparations will also be discussed in the chapter.