标题: 语音系统低功率低失真三角积分数位类比转换器
Low Power Low Distortion Audio Delta-Sigma DAC
作者: 杨家泰
Yang Chia Tai
洪崇智
Chung-Chih Hung
电信工程研究所
关键字: 三角积分;Delta-Sigma
公开日期: 2006
摘要: 近年来因为语音产品的蓬勃发展,如MP3随声听等等,使得语音系统数位类比转换器成为一个重要的目标。而对于用电池运作的语音系统有几个问题是我们必须注意的。因为功率消耗会影响电池的寿命,所以必须把功率消耗设计的越小越好。另外,为了达到多媒体产品的品质需求,此数位类比转换器必须达到约16位元的高解析度。

三角积分数位类比转换器(Delta-Sigma D/A converter)是一种广泛运用的技术,它能够达到高解析度、降低数位电路部份的操作速度、能够缓和频带外(out-of-band)滤波器的需求以及提高对时脉抖动(clock jitter)的免疫力。使用直接电压转换的切换式电容技术可以减少kT/C杂讯和元件不匹配的影响而不增加功率消耗,而资料加权平均的演算法可以抑制电容之间的不匹配所造成的非线性度。

在此研究中我们将介绍一个15等级量化、三阶的三角积分数位类比转换器,取样频率是44.1千赫兹,输入讯号为18位元,因为超取样比率为64倍,所以主要时脉操作在2.8224百万赫兹,由晶片中心(CIC)提供的台积电(tsmc)标准0.18微米制程中实现。
Audio digital-to-analog converters (DAC) have played an important role recently with the rapid growth of the minidisc players and portable audio devices. There are some main issues for a battery-operated audio system. Power dissipation affects the battery life, so it must be as low as possible. A high resolution of about 16bits is required for the DAC to meet the quality of the media.

The delta-sigma D/A converters have been used extensively. It can achieve high resolution, reduce digital circuit speed, relax the requirements of the out-of-band filter, and enhance immunity to clock jitter. Using the direct charge transfer switched-capacitor technique in the multi-bit reconstruction DAC can reduce kT/C noise and element mismatch without increasing power dissipation. The data weighted averaging algorithm restrains nonlinearity caused by the mismatch of capacitors.

A 15-level quantization, third-order delta-sigma DAC is presented. Its sampling rate is 44.1 kHz with 18-bit input. The main clock is 2.8224 MHz because of the 64X oversampling ratio. This DAC was implemented by TSMC 0.18um CMOS process supported by CIC.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009313623
http://hdl.handle.net/11536/78437
显示于类别:Thesis


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