一個新穎且快速的調整睡眠電晶體尺寸演算法經由使用積分型的靈敏度

Abstract

隨著製程進入深次微米時代，特別是在90奈米以下，因為互補式金屬氧化物半導體(CMOS)隨科技進步尺寸縮小，次臨界電流及閘漏電流呈指數增加，漏電功率已經變成主要的議題。所以，如何節省漏電功率變成很重要的議題。節省漏電功率的方法已經廣被發展，而電源閘是眾多有效方法的其中之一個。 在本篇論文裡，我們發展出一個新穎且快速的方法經由利用積分型的靈敏度去調整睡眠電晶體的尺寸。我們提出的演算法分為兩個階段。在第一個階段，我們利用改善卡洛夫子系統法(IEKS)解睡眠電晶體上的跨壓，在第二個階段則用正確的時域解取代改善卡洛夫子系統法 (IEKS)。為了加速整個最佳化的過程，我們也發展出同時選取多個睡眠電晶體來調整。最後的實驗結果顯示我們的方法勝過目前已知最好的方法，它可以有效且快速的達到我們要的目標。

As the process technology enter the deep sub-micro era, especially below 90nm, leakage power has become a major issue due to the exponential increase of sub-threshold and gate leakage current with CMOS technology scaling. So, how to save leakage power becomes a very important issue. Many methods of save leakage power have been general developed, and power gating is one of the most effective methods. In this thesis, we developed a novel and fast method by using integral sensitivity to size the width of sleep transistors. The purposed algorithm has two stages. In the first stage, we solve the voltage drop of sleep transistors by using Improved Extended Krylov Subspace (IEKS), and in the second stage, we employ time domain solver to replace IEKS. In order to speed up the optimizing procedure, a multiple sleep transistor simultaneously sizing strategy is also developed. The experimental results demonstrate that our method outperforms a state-of-the-art method, it can effective and fast to reach our object.