以Balsa實作之非同步JPEG解碼器

Abstract

非同步電路近幾年來越來越受重視,因為省電節能的需求日益提升, 不僅是受限於有限的電池壽命,也由於全球暖化的憂慮.然而,非同步電路本身不容易設計和驗證.藉著Balsa這設計工具的幫忙,人們可以更快速的把非同步的想法實踐. JPEG解碼器是這次實作的對象,因為它被時間所考驗而且複雜度也不會太差而可以顯示這樣一個設計流程的實際性.另外也加入了一個管線架構來提升最耗時間的IDCT運算.又,四相捆包資料被採用為輸出電路的通訊協定用避免雙軌版本造成多餘的面積浪費.

Asynchronous circuits have been more and more popular these days, since there is an increasingly dire need for more efficient use of energy, resulted from not only limited battery life but also concerns for global warming. However, asynchronous circuits have a nature that renders them difficult to design and verify. With the invention of Balsa programming environment, people can forge their “asynchronous” ideas into reality more easily by the help of its synthesis and simulation tools. A JPEG decoder was chosen as the object of implementation because it was tested by time, as well as sophisticated enough to show the viability of this design flow or methodology. A pipeline structure was also added to hasten computation of the most time-consuming part, the IDCT. Furthermore, the 4-phase bundled data approach was taken in this example to facilitate development and avoid excess area cost generated otherwise by a dual-rail version.