標題: | A Pipelined Asynchronous 8051 Soft-core Implemented with Balsa |
作者: | Chen, Chang-Jiu Cheng, Wei-Min Tsai, Ruei-Fu Tsai, Hung-Yue Wang, Tuan-Chieh 資訊工程學系 Department of Computer Science |
公開日期: | 2008 |
摘要: | Microcontrollers are widely used in many handheld devices and embedded systems. Thus, low power, reliability, and robustness have been becoming the critical issues for these microcontrollers. Asynchronous circuits may be one of the best solutions to answer these problems. It is widely known that the 8051 processor is the most popular 8-bit microcontroller; however, because of its CISC nature, the pipeline is not very easy to implement, especially for asynchronous circuits. In this paper, we propose a novel pipelined asynchronous 8051 microcontroller. The design is implemented with Balsa language which is a CSP-based asynchronous HDL, and synthesized into Xilinx netlist by Balsa synthesis tool. The design is compared with synchronous ones with Xilinx FPGA. |
URI: | http://hdl.handle.net/11536/31887 |
ISBN: | 978-1-4244-2341-5 |
期刊: | 2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2008), VOLS 1-4 |
起始頁: | 976 |
結束頁: | 979 |
顯示於類別: | 會議論文 |