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dc.contributor.author王偉任en_US
dc.contributor.authorWei-Ren Wangen_US
dc.contributor.author許騰尹en_US
dc.contributor.authorTerng-Yin Hsuen_US
dc.date.accessioned2014-12-12T02:55:30Z-
dc.date.available2014-12-12T02:55:30Z-
dc.date.issued2008en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT009317625en_US
dc.identifier.urihttp://hdl.handle.net/11536/78837-
dc.description.abstractOrthogonal frequency division multiplexing (OFDM) has been widely adopted in broadband wireless communication systems , such as 802.11a , due to it’s robustness against the effects of multipath propagation. However , OFDM systems are more sensitive to synchronization errors than single carrier systems. Timing synchronization is a crucial part of OFDM receiver design , therefore it’s one of the important tasks performed at the receiver. More specifically ., Sampling Clock Offset (SCO) , if not compensated , could lead to an unacceptable BER increase . The proposed method before to solve sampling clock offset before can tolerate SCO + - 400ppm at most. In this thesis we proposed a method to achieve wider Clock Offset tolerance to 10000 ppm. Our platform is 2-by-2 MIMO-OFDM system set up with matlab. With this platform , our proposed algorithm could be verified and some simulation results will be shown in this thesis. By the accomplishment of these simulations, our algorithm is also verified.zh_TW
dc.description.abstractOrthogonal frequency division multiplexing (OFDM) has been widely adopted in broadband wireless communication systems , such as 802.11a , due to it’s robustness against the effects of multipath propagation. However , OFDM systems are more sensitive to synchronization errors than single carrier systems. Timing synchronization is a crucial part of OFDM receiver design , therefore it’s one of the important tasks performed at the receiver. More specifically ., Sampling Clock Offset (SCO) , if not compensated , could lead to an unacceptable BER increase . The proposed method before to solve sampling clock offset before can tolerate SCO + - 400ppm at most. In this thesis we proposed a method to achieve wider Clock Offset tolerance to 10000 ppm. Our platform is 2-by-2 MIMO-OFDM system set up with matlab. With this platform , our proposed algorithm could be verified and some simulation results will be shown in this thesis. By the accomplishment of these simulations, our algorithm is also verified.en_US
dc.language.isozh_TWen_US
dc.subject時序同步zh_TW
dc.subject時脈漂移zh_TW
dc.subject全數位zh_TW
dc.subjectTiming synchronizationen_US
dc.subjectSampling Clock Offseten_US
dc.subjectAll digitalen_US
dc.title可容忍高時脈誤差之全數位時序同步研究zh_TW
dc.titleThe Study of Digital Timing Recovery For Wide Clock Offset Toleranceen_US
dc.typeThesisen_US
dc.contributor.department資訊科學與工程研究所zh_TW
Appears in Collections:Thesis


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