標題: | 可容忍高時脈誤差之全數位時序同步研究 The Study of Digital Timing Recovery For Wide Clock Offset Tolerance |
作者: | 王偉任 Wei-Ren Wang 許騰尹 Terng-Yin Hsu 資訊科學與工程研究所 |
關鍵字: | 時序同步;時脈漂移;全數位;Timing synchronization;Sampling Clock Offset;All digital |
公開日期: | 2008 |
摘要: | Orthogonal frequency division multiplexing (OFDM) has been widely adopted in broadband wireless communication systems , such as 802.11a , due to it’s robustness against the effects of multipath propagation. However , OFDM systems are more sensitive to synchronization errors than single carrier systems. Timing synchronization is a crucial part of OFDM receiver design , therefore it’s one of the important tasks performed at the receiver. More specifically ., Sampling Clock Offset (SCO) , if not compensated , could lead to an unacceptable BER increase .
The proposed method before to solve sampling clock offset before can tolerate SCO + - 400ppm at most. In this thesis we proposed a method to achieve wider Clock Offset tolerance to 10000 ppm. Our platform is 2-by-2 MIMO-OFDM system set up with matlab. With this platform , our proposed algorithm could be verified and some simulation results will be shown in this thesis. By the accomplishment of these simulations, our algorithm is also verified. Orthogonal frequency division multiplexing (OFDM) has been widely adopted in broadband wireless communication systems , such as 802.11a , due to it’s robustness against the effects of multipath propagation. However , OFDM systems are more sensitive to synchronization errors than single carrier systems. Timing synchronization is a crucial part of OFDM receiver design , therefore it’s one of the important tasks performed at the receiver. More specifically ., Sampling Clock Offset (SCO) , if not compensated , could lead to an unacceptable BER increase . The proposed method before to solve sampling clock offset before can tolerate SCO + - 400ppm at most. In this thesis we proposed a method to achieve wider Clock Offset tolerance to 10000 ppm. Our platform is 2-by-2 MIMO-OFDM system set up with matlab. With this platform , our proposed algorithm could be verified and some simulation results will be shown in this thesis. By the accomplishment of these simulations, our algorithm is also verified. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT009317625 http://hdl.handle.net/11536/78837 |
顯示於類別: | 畢業論文 |