微電子65奈米世代後銅薄膜阻抗係數之探討

Abstract

當電子元件繼續隨著Moore定律從0.25 um世代縮小至65 nm世代時， 銅導線的阻抗係數呈非線性增加，如此對RC (電阻x電容)延遲有負面影響。基本上銅阻抗係數增高可能經由下列數種不同的散射機制 : (1) 表面散射:由銅界面上表面粗糙度與蝕刻造成的粗糙度引起，(2)晶粒大小改變引起的間界散射， (3)缺陷與雜質散射。本論文研究乃利用平面式薄膜疊層來探討各散射的貢獻，其第一目的是探討晶粒大小造成的晶界散射，對阻抗係數上升所造成的影響，第二目的是在固定晶粒大小的情況下來研究表面散射所造成的影響，實驗已成功驗證在線寬90 nm時晶界散射乃是造成阻抗係數上升的主要原因，但是在線寬縮小到60 nm後，表面散射的比例也逐漸爬升。

As device continues scaling down to 65 nm node, the copper line resistance is seen to rise non-linearly, which has negative impact on RC delay. Fundamentally, several parameters may contribute to the copper resistivity increase through different scattering mechanisms such as (1) surface scattering arisen from surface roughness (2) grain boundary scattering by smaller grain size, and (3) defect and impurity scattering. Our research efforts have focused on blanket film stack to understand the scattering contributions. The objective of this study is to quantify the impacts of grain size for grain boundary scattering. The other objective of this study is to quantify the impact of surface scattering by keeping the grain size the same in various film thicknesses. Grain boundary play important role in resistivity increase for thickness between 200 nm and 90 nm, while surface scattering effect become more important for thickness below 60 nm node and below.