覆晶封裝銲錫接點在電遷移效應下之熱與電特性

Abstract

覆晶封裝銲錫接點的電遷移與熱遷移是可靠度上的重要議題，是故了解覆晶封裝銲錫接點的熱電效應相當重要。本研究利用實驗與有限元素分析法研究銲錫接點在測試時的熱電特徵。首先利用聚焦離子束製備出具有記號的銲錫接點，驗證出電遷移速率與電流密度呈現正比的關係；再者因為四點量測的結構改用，可以使得凸塊電阻可直接量測出來，並且在不同位置量測到的電阻有所不同；隨著電遷移產生孔洞並成長，使得電流密度與溫度重新分佈的情形都可以利用模擬得知，會發現銲錫接點內部的電流密度與溫度在孔洞生成50%時，會先些許下降，當孔洞持續成長的時候，電流密度與溫度會改為上升；此外利用不同線寬的導線研究導線寬度對電遷移壽命的影響，發現導線線寬會影響電流集中效應與焦耳熱效應，但主要還是熱的影響，使得線寬比較寬的時候，壽命得以延長；另外還討論銲錫接點在通電後期造成的熔化，主要是來自於導線的劣化損壞，使得溫度急遽上升達到熔點；最後，因為電流集中效應的關係，使得覆晶封裝銲錫接點內部的溫度呈現非線性分佈。 另外利用模擬的結果討論利用變換底部金屬層材料、鋁導線設計、底部金屬層厚度以及接觸窗口大小，設法找出覆晶封裝銲錫接點之最佳化結構，以供後續設計之參考。最後在分析當銲錫接點越做越小時，對溫度與電流密度之影響，並對矽晶片在三度空間堆疊下，將會減薄矽晶片厚度，而當矽晶片變薄之下，對銲錫接點溫度之影響。此些議題將在此研究裡詳細地討論。

Electromigration and thermomigration are two important issues in flip-chip solder joints under current stressing. Thus, to investigate the current density and temperature distribution is quite valuable. In this study, the experiments and finite-elements method were used to understand the thermo-electrical characterizations in flip-chip solder bumps under current stressing. The observation of marker movement made by focused ion beam (FIB) confirmed that the electromigration flux is proportional to the current density. Using the four-point probing, the bump resistance was measured directly. Also, the bump resistance changed due to the change of measuring position. Due to the void formation and propagation, the current density and temperature re-distributed. Before the voids grew and became 50% of the contact opening, the current density and temperature decreased slightly. When the voids continuously grew, the current density and temperature increased. The width of Al trace affected the current crowding and Joule heating effect in the flip-chip solder joints. The main effect on mean-time-to-failure (MTTF) is the Joule heating effect. Then, the key reason causing the solder melting at the final stressing period is the degradation of Al trace. Rapid increase in Al trace resistance caused the abrupt Joule heating to melt the solder bumps. The non-linear thermal gradient was found in flip-chip solder joints under current stressing due to current crowding effect. In addition, the simulation study was carried out in order to find the suitable UBM material, Al trace’s designation, the thickness of UBM and the size of contact opening, so as to determine the optimal structure of flip-chip solder joints. These results are useful guidelines for later designation. Afterward, to analyze its effects on temperature and electric current density when the size of flip-chip solder joints shrink. When pilling up in three dimensions, Si chip will be thinner, the effect of this change on flip-chip solder joints will thoroughly be discussed as well.