氧化鉿閘極介電層之氟鈍化製程與應力工程的研究

Abstract

首先，我們提出多種氟鈍化(passivatation)技術以製作高效能且高可靠度的二氧化鉿閘極絕緣層(HfO2 gate dielectrics)。接著研究經過氟化之氧化鉿其電流穿遂機制(current transportation mechanism)與載子捕捉(charge trapping)特性。最後，我們發現氮化矽所引發的應力(strain)矽通道之氧化鉿電晶體，其可靠度以及元件特性都獲得大幅度的改善 一開始我們提出了以矽表面氟離子植入法(silicon surface fluorine implantation)，將氟離子導入二氧化鉿薄膜以及此二氧化鉿薄膜與矽基板之介面處。從實驗結果可以充分證明此氟化二氧化鉿薄膜會擁有較好的熱穩定性，此氟化二氧化鉿薄膜的漏電流會比一般傳統的二氧化鉿還低了三個數量級，此外，應力下所導致的漏電流(stress-induced leakage current)以及電荷捕捉(charge trapping)的問題都可以藉由此氟離子佈值法來使得此二氧化鉿閘極介電層有更好的特性。此氟原子與二氧化鉿薄膜混合不僅僅可以減少介面狀態的懸空鍵結(interface dangling bond)還可以有效減少此薄膜層的電荷捕捉情形，而進一步的有效改善二氧化鉿薄膜的特性。另ㄧ方面，我們進一步研究氟化氧化鉿閘極介電層其電流傳導機制。我們利用變溫量測的漏電流變化以及低溫(77 K)量測的漏電流來分析電流傳導特性以及此電容元件的能帶圖(energy band diagrams)，從實驗結果中可以發現氟化介面層與矽基板的傳導帶落差(conduction band offset)有3.2 eV而傳統介面層的落差則只有2.7 eV；氟化二氧化鉿與金屬閘極的傳導帶落差有2.6 eV而傳統二氧化鉿的落差則只有1.9 eV；不論是閘極注入(gate injection)模式或基板注入(substrate injection)模式操作，氟化二氧化鉿的有效載子捕捉深度大約是低於介電層傳導帶1.25 eV，而傳統的二氧化鉿在閘極注入模式下的有效載子捕捉深度大約是低於介電層傳導帶1.04 eV，而在基板注入模式下的有效載子捕捉深度大約是低於介電層傳導帶1.11 eV。 此外，我們提出與現有製程具高度匹配性的四氟化碳電漿處理(CF4 plasma treatment)技術，用以製作高效能的二氧化鉿閘極絕緣層之電容。此技術可分類成兩種：首先藉由前處理的技術，我們可以有效的抑制高介電閘極絕緣層電容中的介面層(interfacial layer)生長，藉此得到更薄的等效氧化層厚度(effective oxide thickness)，除此之外，還可以有效的抑制矽化鉿的形成並產生鉿-氟鍵結(Hf-F bonding)。接著利用四氟化碳電漿後處理的技術，氟原子可以有效地被導入二氧化鉿薄膜以及此二氧化鉿薄膜與矽基板之介面以消除薄膜中的載子補獲態(trap states)，並進而有效地改善此閘極絕緣層的介面特性。經由四氟化碳電漿處理的二氧化鉿閘極絕緣層之電容具有較低的漏電流、高的崩潰電壓及較薄的等效氧化層厚度(effective oxide thickness)；其磁滯現象(hysteresis)更大幅改善了超過 90 %。此外，我們更進一步提出物理模型來解釋此磁滯效應的改善機制。 接著我們提出新穎之氟化氧化鉿電晶體，利用四氟化碳電漿處理，可同時改善n型及p型氧化鉿電晶體，相當適用於新型互補式金氧半場效電晶體的製作。此電晶體有相當高水準的表現及可靠度：高達6.69×107的導通電流與關閉電流之比例、 接近76 mV/dec的次臨界擺幅、小於20 mV的源極引發能障衰退以及相當高的載子遷移率(~165 cm2/V．s)。此氟化氧化鉿電晶體有較佳的介面特性及品質較好的絕緣層：較小的閘極引發汲極漏電流(gate induced drain leakage)以及較低的正偏壓溫度所引起的元件不穩定性。而造成此特性及可靠度改善的原因是來自於氟原子導入二氧化鉿薄膜以及此二氧化鉿薄膜與矽基板之介面，進一步減少介電層的缺陷且抑制電子電洞對的產生，並導致絕緣層有較深的載子捕捉位置及減少載子捕捉情形的發生。 最後，我們首度對於氮化矽所引發的應變矽通道之氧化鉿電晶體提出新的發現，可靠度以及元件特性都獲得大幅度的改善，此外，我們利用脈衝型量測系統去分析此氧化鉿電晶體接近真實的特性，發現有百分之九十的驅動電流增加以及百分之五十的轉移電導的提升。而此應變矽通道的氧化鉿電晶體會擁有較佳的介面特性以及較低的正偏壓溫度所引起的元件不穩定性，其元件的充電電流泵(charge pumping current)有大約百分之九十的減少且正偏壓溫度所引起的元件不穩定性效應也降低了百分之五十五。之後我們利用動態臨限電壓(dynamic threshold)操作法來提升應變矽通道的氧化鉿電晶體的元件特性，發現轉移電導有高達百分之ㄧ百三十五的增加，且次臨界擺幅有接近理想的表現(~62 cm2/V．s)，在元件特性獲得大幅提升的同時，其可靠度亦維持可容忍的劣化表現。

First, we demonstrated several fluorine passivation technologies to fabricate high performance and highly reliable HfO2 gate dielectrics. Then, we investigated the current transportation and charge trapping mechanism of fluorinated HfO2 gate dielectrics. Finally, new observation on improved characteristics and PBTI reliability of contact etching stop layer induced local tensile strained nMOSFETs with HfO2 gate dielectrics were reported At beginning, we describe the characteristics of silicon surface fluorine implantation (SSFI) for HfO2 films with high-temperature postdeposition annealing. The thermal stability of HfO2 gate dielectrics is much improved owing to the incorporation of fluorine into HfO2 thin films. The gate leakage current of the SSFI HfO2 films is about three orders less than that of samples without any fluorine implantation. In addition, improvements in stress-induced leakage current (SILC) and charge trapping characteristics are realized in the HfO2 films with the SSFI. The incorporation of fluorine atoms into the HfO2 films reduces not only interface dangling bonds but also bulk traps, which is responsible for the improvements in properties. On the other hand, the current transportation mechanism of HfO2 gate dielectrics with TaN metal gate and silicon surface fluorine implantation (SSFI) is also investigated. Based on the experimental results of the temperature dependence of gate leakage current and Fowler–Nordheim tunneling characteristics at 77 K, we have extracted the current transport mechanisms and energy band diagrams for TaN/HfO2/IL/Si structures with fluorine incorporation, respectively. In particular, we have obtained the following physical quantities: i) fluorinated and as-deposited IL/Si barrier heights (or conduction band offset): 3.2 eV & 2.7 eV; ii) TaN/ fluorinated and as-deposited HfO2 barrier height: 2.6 eV & 1.9 eV; and iii) effective trapping levels at 1.25 eV (under both gate and substrate injections) below the HfOF conduction band, 1.04 eV (under gate injection) and 1.11 eV (under substrate injection) below the HfO2 conduction band, which contributes to Frenkel–Poole conduction. In addition, a process-compatible CF4 plasma treatment for fabricating high-performance HfO2 gate dielectrics MOS capacitor is demonstrated. This CF4 plasma treatment was divided into two parts, which are pre-CF4 plasma treatment and post-CF4 plasma treatment, respectively. The effective oxide thickness of high-k gate dielectrics was much reduced by using the pre-CF4 plasma treatment due to the elimination of the interfacial layer between HfO2 and Si-substrate. In addition, the Hf-silicide was suppressed and Hf-F bonding was observed for the CF4 plasma pre-treated sample. On the other hand, the fluorine atoms were effectively incorporated into HfO2 thin film and HfO2/Si interface by post-CF4 plasma treatment. The charge trapping would be eliminated and the interface of the HfO2 gate dielectrics was also improved. The device post-treated by CF4 plasma treatment would have low leakage current, higher breakdown voltage, and thinner effective oxide thickness. Besides, the C-V hysteresis was much reduced about 90 %. A physical model was presented to explain the improvement of hysteresis phenomenon and the elimination of charge trapping of the fluorinated HfO2 gate dielectrics. Then, a novel high-performance and excellent-reliability HfOF MOSFET was demonstrated. Both n and p-type HfOF MOSFET can be improved by CF4 plasma treatment, indicating this technique is compatible with CMOS fabrication. Large ION/Imin current ratio (~6.69×107), good Subthreshold Swing (~76 mV/dec), small DIBL (<20 mV), and high mobility (~165 cm2/V．s) can be observed for the HfOF nMOSFETs. The HfOF nMOSFET has better HfO2/Si interface and dielectric quality, including small GIDL current and less PBTI effect. Reduced GIDL current was observed for the HfOF nMOSFET due to HfO2/Si interface passivation by fluorine, resulting in less hole-electron pair generation. The fluorine incorporation into HfO2 gate dielectrics effectively passivated the dielectric vacancies, resulting in a deeper trapping cross section and a lower concentration of generated traps. Finally, new observation on SiN-cap strain-induced improved characteristics and PBTI reliability of nMOSFETs with HfO2 gate dielectrics were reported for the first time. The “close-to-intrinsic” characteristics including driving current and gm of SiN-capped HfO2 nMOSFETs were much enhanced about 90% and 50%, respectively by pulse-IV measurement. The CESL-device has better HfO2/Si interface and dielectric quality, including less charge pumping current (90% reduction) and less PBTI effect (55% reduction). Finally, the performance of CESL-HfO2 nMOSFETs will have larger gm (135% increase) and “close-to-ideal” subthresold swing (~62) using dynamic threshold (DT) operation mode with tolerant hot carrier-stress characterization. These results provide a valuable guideline for the future 45 nm and beyond CMOS device design with high-k and strain engineering.