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dc.contributor.authorLu, Tsung Yien_US
dc.contributor.authorWang, Chin Mengen_US
dc.contributor.authorChao, Tien-Shengen_US
dc.date.accessioned2014-12-08T15:10:21Z-
dc.date.available2014-12-08T15:10:21Z-
dc.date.issued2009en_US
dc.identifier.issn1099-0062en_US
dc.identifier.urihttp://hdl.handle.net/11536/7909-
dc.identifier.urihttp://dx.doi.org/10.1149/1.3005556en_US
dc.description.abstractAn enhanced stress memorization-technique that utilizes a strain proximity free technique (SPFT) and a stacked-gate structure has been demonstrated by multiple strain-gate engineering. The electron mobility of n-channel metal-oxide semiconductor field effect transistors (nMOSFETs) with SPFT exhibit a 16% increase compared to that of counterpart techniques. SPFT avoids the limitation of stressor volume for performance improvement in high-density complementary metal oxide semiconductor circuits. We also found that optimization of stacked, random poly-Si-grain gate structure in combination with SPFT can improve mobility further to 22% more than a single poly-Si gate structure without SPFT.en_US
dc.language.isoen_USen_US
dc.subjectCMOS integrated circuitsen_US
dc.subjectelectron mobilityen_US
dc.subjectelemental semiconductorsen_US
dc.subjecthot carriersen_US
dc.subjectMOSFETen_US
dc.subjectreliabilityen_US
dc.subjectsiliconen_US
dc.titleEnhancement of Stress-Memorization Technique on nMOSFETs by Multiple Strain-Gate Engineeringen_US
dc.typeArticleen_US
dc.identifier.doi10.1149/1.3005556en_US
dc.identifier.journalELECTROCHEMICAL AND SOLID STATE LETTERSen_US
dc.citation.volume12en_US
dc.citation.issue1en_US
dc.citation.spageH4en_US
dc.citation.epageH6en_US
dc.contributor.department電子物理學系zh_TW
dc.contributor.departmentDepartment of Electrophysicsen_US
dc.identifier.wosnumberWOS:000260873700013-
dc.citation.woscount2-
Appears in Collections:Articles